10bc18309SAnson Huang /* 20bc18309SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 30bc18309SAnson Huang * 40bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 50bc18309SAnson Huang */ 60bc18309SAnson Huang 70bc18309SAnson Huang #include <arch.h> 80bc18309SAnson Huang #include <arch_helpers.h> 90bc18309SAnson Huang #include <debug.h> 100bc18309SAnson Huang #include <gicv3.h> 110bc18309SAnson Huang #include <mmio.h> 120bc18309SAnson Huang #include <plat_imx8.h> 130bc18309SAnson Huang #include <psci.h> 140bc18309SAnson Huang #include <sci/sci.h> 150bc18309SAnson Huang #include <stdbool.h> 160bc18309SAnson Huang 170bc18309SAnson Huang const static int ap_core_index[PLATFORM_CORE_COUNT] = { 180bc18309SAnson Huang SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 190bc18309SAnson Huang }; 200bc18309SAnson Huang 210bc18309SAnson Huang plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 220bc18309SAnson Huang const plat_local_state_t *target_state, 230bc18309SAnson Huang unsigned int ncpu) 240bc18309SAnson Huang { 250bc18309SAnson Huang return 0; 260bc18309SAnson Huang } 270bc18309SAnson Huang 280bc18309SAnson Huang int imx_pwr_domain_on(u_register_t mpidr) 290bc18309SAnson Huang { 300bc18309SAnson Huang int ret = PSCI_E_SUCCESS; 310bc18309SAnson Huang unsigned int cpu_id; 320bc18309SAnson Huang 330bc18309SAnson Huang cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 340bc18309SAnson Huang 350bc18309SAnson Huang tf_printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); 360bc18309SAnson Huang 370bc18309SAnson Huang if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 380bc18309SAnson Huang SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 390bc18309SAnson Huang ERROR("core %d power on failed!\n", cpu_id); 400bc18309SAnson Huang ret = PSCI_E_INTERN_FAIL; 410bc18309SAnson Huang } 420bc18309SAnson Huang 430bc18309SAnson Huang if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 440bc18309SAnson Huang true, BL31_BASE) != SC_ERR_NONE) { 450bc18309SAnson Huang ERROR("boot core %d failed!\n", cpu_id); 460bc18309SAnson Huang ret = PSCI_E_INTERN_FAIL; 470bc18309SAnson Huang } 480bc18309SAnson Huang 490bc18309SAnson Huang return ret; 500bc18309SAnson Huang } 510bc18309SAnson Huang 520bc18309SAnson Huang void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 530bc18309SAnson Huang { 540bc18309SAnson Huang plat_gic_pcpu_init(); 550bc18309SAnson Huang plat_gic_cpuif_enable(); 560bc18309SAnson Huang } 570bc18309SAnson Huang 580bc18309SAnson Huang int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 590bc18309SAnson Huang { 600bc18309SAnson Huang return PSCI_E_SUCCESS; 610bc18309SAnson Huang } 620bc18309SAnson Huang 630bc18309SAnson Huang static const plat_psci_ops_t imx_plat_psci_ops = { 640bc18309SAnson Huang .pwr_domain_on = imx_pwr_domain_on, 650bc18309SAnson Huang .pwr_domain_on_finish = imx_pwr_domain_on_finish, 660bc18309SAnson Huang .validate_ns_entrypoint = imx_validate_ns_entrypoint, 678972694eSAnson Huang .system_off = imx_system_off, 68*351e3731SAnson Huang .system_reset = imx_system_reset, 690bc18309SAnson Huang }; 700bc18309SAnson Huang 710bc18309SAnson Huang int plat_setup_psci_ops(uintptr_t sec_entrypoint, 720bc18309SAnson Huang const plat_psci_ops_t **psci_ops) 730bc18309SAnson Huang { 740bc18309SAnson Huang imx_mailbox_init(sec_entrypoint); 750bc18309SAnson Huang *psci_ops = &imx_plat_psci_ops; 760bc18309SAnson Huang 770bc18309SAnson Huang return 0; 780bc18309SAnson Huang } 79