1*0bc18309SAnson Huang /* 2*0bc18309SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*0bc18309SAnson Huang * 4*0bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*0bc18309SAnson Huang */ 6*0bc18309SAnson Huang 7*0bc18309SAnson Huang #include <arch.h> 8*0bc18309SAnson Huang #include <arch_helpers.h> 9*0bc18309SAnson Huang #include <debug.h> 10*0bc18309SAnson Huang #include <gicv3.h> 11*0bc18309SAnson Huang #include <mmio.h> 12*0bc18309SAnson Huang #include <plat_imx8.h> 13*0bc18309SAnson Huang #include <psci.h> 14*0bc18309SAnson Huang #include <sci/sci.h> 15*0bc18309SAnson Huang #include <stdbool.h> 16*0bc18309SAnson Huang 17*0bc18309SAnson Huang const static int ap_core_index[PLATFORM_CORE_COUNT] = { 18*0bc18309SAnson Huang SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 19*0bc18309SAnson Huang }; 20*0bc18309SAnson Huang 21*0bc18309SAnson Huang plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 22*0bc18309SAnson Huang const plat_local_state_t *target_state, 23*0bc18309SAnson Huang unsigned int ncpu) 24*0bc18309SAnson Huang { 25*0bc18309SAnson Huang return 0; 26*0bc18309SAnson Huang } 27*0bc18309SAnson Huang 28*0bc18309SAnson Huang int imx_pwr_domain_on(u_register_t mpidr) 29*0bc18309SAnson Huang { 30*0bc18309SAnson Huang int ret = PSCI_E_SUCCESS; 31*0bc18309SAnson Huang unsigned int cpu_id; 32*0bc18309SAnson Huang 33*0bc18309SAnson Huang cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 34*0bc18309SAnson Huang 35*0bc18309SAnson Huang tf_printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); 36*0bc18309SAnson Huang 37*0bc18309SAnson Huang if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 38*0bc18309SAnson Huang SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 39*0bc18309SAnson Huang ERROR("core %d power on failed!\n", cpu_id); 40*0bc18309SAnson Huang ret = PSCI_E_INTERN_FAIL; 41*0bc18309SAnson Huang } 42*0bc18309SAnson Huang 43*0bc18309SAnson Huang if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 44*0bc18309SAnson Huang true, BL31_BASE) != SC_ERR_NONE) { 45*0bc18309SAnson Huang ERROR("boot core %d failed!\n", cpu_id); 46*0bc18309SAnson Huang ret = PSCI_E_INTERN_FAIL; 47*0bc18309SAnson Huang } 48*0bc18309SAnson Huang 49*0bc18309SAnson Huang return ret; 50*0bc18309SAnson Huang } 51*0bc18309SAnson Huang 52*0bc18309SAnson Huang void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 53*0bc18309SAnson Huang { 54*0bc18309SAnson Huang plat_gic_pcpu_init(); 55*0bc18309SAnson Huang plat_gic_cpuif_enable(); 56*0bc18309SAnson Huang } 57*0bc18309SAnson Huang 58*0bc18309SAnson Huang int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 59*0bc18309SAnson Huang { 60*0bc18309SAnson Huang return PSCI_E_SUCCESS; 61*0bc18309SAnson Huang } 62*0bc18309SAnson Huang 63*0bc18309SAnson Huang static const plat_psci_ops_t imx_plat_psci_ops = { 64*0bc18309SAnson Huang .pwr_domain_on = imx_pwr_domain_on, 65*0bc18309SAnson Huang .pwr_domain_on_finish = imx_pwr_domain_on_finish, 66*0bc18309SAnson Huang .validate_ns_entrypoint = imx_validate_ns_entrypoint, 67*0bc18309SAnson Huang }; 68*0bc18309SAnson Huang 69*0bc18309SAnson Huang int plat_setup_psci_ops(uintptr_t sec_entrypoint, 70*0bc18309SAnson Huang const plat_psci_ops_t **psci_ops) 71*0bc18309SAnson Huang { 72*0bc18309SAnson Huang imx_mailbox_init(sec_entrypoint); 73*0bc18309SAnson Huang *psci_ops = &imx_plat_psci_ops; 74*0bc18309SAnson Huang 75*0bc18309SAnson Huang return 0; 76*0bc18309SAnson Huang } 77