1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/console.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <plat/common/platform.h> 22 23 #include <imx8qx_pads.h> 24 #include <imx8_iomux.h> 25 #include <imx8_lpuart.h> 26 #include <plat_imx8.h> 27 #include <sci/sci.h> 28 #include <sec_rsrc.h> 29 30 static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; 31 static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; 32 static const unsigned long BL31_RO_START = BL_CODE_BASE; 33 static const unsigned long BL31_RO_END = BL_CODE_END; 34 static const unsigned long BL31_RW_END = BL_END; 35 36 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 37 38 static entry_point_info_t bl32_image_ep_info; 39 static entry_point_info_t bl33_image_ep_info; 40 41 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \ 42 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ 43 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ 44 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ 45 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) 46 47 static const mmap_region_t imx_mmap[] = { 48 MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW), 49 {0} 50 }; 51 52 static uint32_t get_spsr_for_bl33_entry(void) 53 { 54 unsigned long el_status; 55 unsigned long mode; 56 uint32_t spsr; 57 58 /* figure out what mode we enter the non-secure world */ 59 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 60 el_status &= ID_AA64PFR0_ELX_MASK; 61 62 mode = (el_status) ? MODE_EL2 : MODE_EL1; 63 64 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 65 return spsr; 66 } 67 68 #if DEBUG_CONSOLE_A35 69 static void lpuart32_serial_setbrg(unsigned int base, int baudrate) 70 { 71 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr; 72 unsigned int diff1, diff2, tmp, rate; 73 74 if (baudrate == 0) 75 panic(); 76 77 sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 78 79 baud_diff = baudrate; 80 osr = 0; 81 sbr = 0; 82 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 83 tmp_sbr = (rate / (baudrate * tmp_osr)); 84 if (tmp_sbr == 0) 85 tmp_sbr = 1; 86 87 /* calculate difference in actual baud w/ current values */ 88 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; 89 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); 90 91 /* select best values between sbr and sbr+1 */ 92 if (diff1 > (baudrate - diff2)) { 93 diff1 = baudrate - diff2; 94 tmp_sbr++; 95 } 96 97 if (diff1 <= baud_diff) { 98 baud_diff = diff1; 99 osr = tmp_osr; 100 sbr = tmp_sbr; 101 } 102 } 103 104 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); 105 106 if ((osr > 3) && (osr < 8)) 107 tmp |= LPUART_BAUD_BOTHEDGE_MASK; 108 109 tmp &= ~LPUART_BAUD_OSR_MASK; 110 tmp |= LPUART_BAUD_OSR(osr - 1); 111 tmp &= ~LPUART_BAUD_SBR_MASK; 112 tmp |= LPUART_BAUD_SBR(sbr); 113 114 /* explicitly disable 10 bit mode & set 1 stop bit */ 115 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); 116 117 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); 118 } 119 120 static int lpuart32_serial_init(unsigned int base) 121 { 122 unsigned int tmp; 123 124 /* disable TX & RX before enabling clocks */ 125 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 126 tmp &= ~(CTRL_TE | CTRL_RE); 127 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 128 129 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); 130 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); 131 132 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); 133 134 /* provide data bits, parity, stop bit, etc */ 135 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); 136 137 /* eight data bits no parity bit */ 138 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 139 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); 140 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 141 142 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE); 143 144 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 145 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 146 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); 147 148 return 0; 149 } 150 #endif 151 152 void imx8_partition_resources(void) 153 { 154 sc_rm_pt_t secure_part, os_part; 155 sc_rm_mr_t mr, mr_record = 64; 156 sc_faddr_t start, end; 157 sc_err_t err; 158 bool owned; 159 int i; 160 161 err = sc_rm_get_partition(ipc_handle, &secure_part); 162 if (err) 163 ERROR("sc_rm_get_partition failed: %u\n", err); 164 165 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false, 166 false, false, false); 167 if (err) 168 ERROR("sc_rm_partition_alloc failed: %u\n", err); 169 170 err = sc_rm_set_parent(ipc_handle, os_part, secure_part); 171 if (err) 172 ERROR("sc_rm_set_parent: %u\n", err); 173 174 /* set secure resources to NOT-movable */ 175 for (i = 0; i < (ARRAY_SIZE(secure_rsrcs)); i++) { 176 err = sc_rm_set_resource_movable(ipc_handle, 177 secure_rsrcs[i], secure_rsrcs[i], false); 178 if (err) 179 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 180 secure_rsrcs[i], err); 181 } 182 183 /* move all movable resources and pins to non-secure partition */ 184 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true); 185 if (err) 186 ERROR("sc_rm_move_all: %u\n", err); 187 188 /* iterate through peripherals to give NS OS part access */ 189 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { 190 err = sc_rm_set_peripheral_permissions(ipc_handle, 191 ns_access_allowed[i], os_part, SC_RM_PERM_FULL); 192 if (err) 193 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \ 194 ret %u\n", ns_access_allowed[i], err); 195 } 196 197 /* 198 * sc_rm_set_peripheral_permissions 199 * sc_rm_set_memreg_permissions 200 * sc_rm_set_pin_movable 201 */ 202 for (mr = 0; mr < 64; mr++) { 203 owned = sc_rm_is_memreg_owned(ipc_handle, mr); 204 if (owned) { 205 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end); 206 if (err) 207 ERROR("Memreg get info failed, %u\n", mr); 208 209 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end); 210 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { 211 mr_record = mr; /* Record the mr for ATF running */ 212 } else { 213 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 214 if (err) 215 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \ 216 err %d\n", start, end, err); 217 } 218 } 219 } 220 221 if (mr_record != 64) { 222 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end); 223 if (err) 224 ERROR("Memreg get info failed, %u\n", mr_record); 225 if ((BL31_LIMIT - 1) < end) { 226 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); 227 if (err) 228 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 229 (sc_faddr_t)BL31_LIMIT, end); 230 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 231 if (err) 232 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 233 (sc_faddr_t)BL31_LIMIT, end); 234 } 235 236 if (start < (BL31_BASE - 1)) { 237 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1); 238 if (err) 239 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 240 start, (sc_faddr_t)BL31_BASE - 1); 241 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 242 if (err) 243 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 244 start, (sc_faddr_t)BL31_BASE - 1); 245 } 246 } 247 248 if (err) 249 NOTICE("Partitioning Failed\n"); 250 else 251 NOTICE("Non-secure Partitioning Succeeded\n"); 252 } 253 254 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 255 u_register_t arg2, u_register_t arg3) 256 { 257 #if DEBUG_CONSOLE 258 static console_lpuart_t console; 259 #endif 260 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) 261 panic(); 262 263 #if DEBUG_CONSOLE_A35 264 sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); 265 sc_pm_clock_rate_t rate = 80000000; 266 sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 267 sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); 268 269 /* Configure UART pads */ 270 sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); 271 sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); 272 lpuart32_serial_init(IMX_BOOT_UART_BASE); 273 #endif 274 275 #if DEBUG_CONSOLE 276 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 277 IMX_CONSOLE_BAUDRATE, &console); 278 #endif 279 /* Turn on MU1 for non-secure OS/Hypervisor */ 280 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); 281 282 /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */ 283 sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); 284 sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); 285 mmio_write_32(IMX_GPT0_LPCG_BASE, mmio_read_32(IMX_GPT0_LPCG_BASE) | (1 << 25)); 286 287 /* 288 * create new partition for non-secure OS/Hypervisor 289 * uses global structs defined in sec_rsrc.h 290 */ 291 imx8_partition_resources(); 292 293 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 294 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 295 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 296 } 297 298 void bl31_plat_arch_setup(void) 299 { 300 unsigned long ro_start = BL31_RO_START; 301 unsigned long ro_size = BL31_RO_END - BL31_RO_START; 302 unsigned long rw_start = BL31_RW_START; 303 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 304 #if USE_COHERENT_MEM 305 unsigned long coh_start = BL31_COHERENT_RAM_START; 306 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START; 307 #endif 308 309 mmap_add_region(ro_start, ro_start, ro_size, 310 MT_RO | MT_MEMORY | MT_SECURE); 311 mmap_add_region(rw_start, rw_start, rw_size, 312 MT_RW | MT_MEMORY | MT_SECURE); 313 mmap_add(imx_mmap); 314 315 #if USE_COHERENT_MEM 316 mmap_add_region(coh_start, coh_start, coh_size, 317 MT_DEVICE | MT_RW | MT_SECURE); 318 #endif 319 320 init_xlat_tables(); 321 enable_mmu_el3(0); 322 } 323 324 void bl31_platform_setup(void) 325 { 326 plat_gic_driver_init(); 327 plat_gic_init(); 328 } 329 330 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 331 { 332 if (type == NON_SECURE) 333 return &bl33_image_ep_info; 334 if (type == SECURE) 335 return &bl32_image_ep_info; 336 337 return NULL; 338 } 339 340 unsigned int plat_get_syscnt_freq2(void) 341 { 342 return COUNTER_FREQUENCY; 343 } 344 345 void bl31_plat_runtime_setup(void) 346 { 347 return; 348 } 349