1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 8 #define PLATFORM_LINKER_ARCH aarch64 9 10 #define PLATFORM_STACK_SIZE 0X400 11 #define CACHE_WRITEBACK_GRANULE 64 12 13 #define PLAT_PRIMARY_CPU 0x0 14 #define PLATFORM_MAX_CPU_PER_CLUSTER 4 15 #define PLATFORM_CLUSTER_COUNT 2 16 #define PLATFORM_CLUSTER0_CORE_COUNT 4 17 #define PLATFORM_CLUSTER1_CORE_COUNT 2 18 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 19 PLATFORM_CLUSTER1_CORE_COUNT) 20 21 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 22 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 23 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 24 25 #define PWR_DOMAIN_AT_MAX_LVL 1 26 #define PLAT_MAX_PWR_LVL 2 27 #define PLAT_MAX_OFF_STATE 2 28 #define PLAT_MAX_RET_STATE 1 29 30 #define BL31_BASE 0x80000000 31 #define BL31_LIMIT 0x80020000 32 33 #define PLAT_GICD_BASE 0x51a00000 34 #define PLAT_GICD_SIZE 0x10000 35 #define PLAT_GICR_BASE 0x51b00000 36 #define PLAT_GICR_SIZE 0xc0000 37 #define PLAT_CCI_BASE 0x52090000 38 #define PLAT_CCI_SIZE 0x10000 39 #define CLUSTER0_CCI_SLVAE_IFACE 3 40 #define CLUSTER1_CCI_SLVAE_IFACE 4 41 #define IMX_BOOT_UART_BASE 0x5a060000 42 #define IMX_BOOT_UART_SIZE 0x1000 43 #define IMX_BOOT_UART_BAUDRATE 115200 44 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 45 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 46 #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 47 #define IMX_CONSOLE_BAUDRATE 115200 48 #define SC_IPC_BASE 0x5d1b0000 49 #define SC_IPC_SIZE 0x10000 50 51 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 52 53 /* non-secure uboot base */ 54 #define PLAT_NS_IMAGE_OFFSET 0x80020000 55 56 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 57 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 58 59 #define MAX_XLAT_TABLES 8 60 #define MAX_MMAP_REGIONS 12 61 62 #define DEBUG_CONSOLE 0 63 #define DEBUG_CONSOLE_A53 0 64 #define PLAT_IMX8QM 1 65