1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <mmio.h> 13 #include <plat_imx8.h> 14 #include <psci.h> 15 #include <sci/sci.h> 16 #include <stdbool.h> 17 18 #define CORE_PWR_STATE(state) \ 19 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 20 #define CLUSTER_PWR_STATE(state) \ 21 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 22 #define SYSTEM_PWR_STATE(state) \ 23 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 24 25 const static int ap_core_index[PLATFORM_CORE_COUNT] = { 26 SC_R_A53_0, SC_R_A53_1, SC_R_A53_2, 27 SC_R_A53_3, SC_R_A72_0, SC_R_A72_1, 28 }; 29 30 int imx_pwr_domain_on(u_register_t mpidr) 31 { 32 int ret = PSCI_E_SUCCESS; 33 unsigned int cluster_id, cpu_id; 34 35 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 36 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 37 38 tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id); 39 40 if (cluster_id == 0) { 41 sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, 42 SC_PM_PW_MODE_ON); 43 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 44 SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 45 ERROR("cluster0 core %d power on failed!\n", cpu_id); 46 ret = PSCI_E_INTERN_FAIL; 47 } 48 49 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 50 true, BL31_BASE) != SC_ERR_NONE) { 51 ERROR("boot cluster0 core %d failed!\n", cpu_id); 52 ret = PSCI_E_INTERN_FAIL; 53 } 54 } else { 55 sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, 56 SC_PM_PW_MODE_ON); 57 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id + 4], 58 SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 59 ERROR(" cluster1 core %d power on failed!\n", cpu_id); 60 ret = PSCI_E_INTERN_FAIL; 61 } 62 63 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id + 4], 64 true, BL31_BASE) != SC_ERR_NONE) { 65 ERROR("boot cluster1 core %d failed!\n", cpu_id); 66 ret = PSCI_E_INTERN_FAIL; 67 } 68 } 69 70 return ret; 71 } 72 73 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 74 { 75 uint64_t mpidr = read_mpidr_el1(); 76 77 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 79 80 plat_gic_pcpu_init(); 81 plat_gic_cpuif_enable(); 82 } 83 84 void imx_pwr_domain_off(const psci_power_state_t *target_state) 85 { 86 u_register_t mpidr = read_mpidr_el1(); 87 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 88 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 89 90 plat_gic_cpuif_disable(); 91 sc_pm_req_cpu_low_power_mode(ipc_handle, 92 ap_core_index[cpu_id + cluster_id * 4], 93 SC_PM_PW_MODE_OFF, 94 SC_PM_WAKE_SRC_NONE); 95 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 96 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 97 tf_printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id); 98 } 99 100 void imx_domain_suspend(const psci_power_state_t *target_state) 101 { 102 u_register_t mpidr = read_mpidr_el1(); 103 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 104 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 105 106 plat_gic_cpuif_disable(); 107 108 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 109 110 sc_pm_set_cpu_resume_addr(ipc_handle, 111 ap_core_index[cpu_id + cluster_id * 4], BL31_BASE); 112 sc_pm_req_cpu_low_power_mode(ipc_handle, 113 ap_core_index[cpu_id + cluster_id * 4], 114 SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); 115 } 116 117 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 118 { 119 u_register_t mpidr = read_mpidr_el1(); 120 121 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 122 123 plat_gic_cpuif_enable(); 124 } 125 126 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 127 { 128 return PSCI_E_SUCCESS; 129 } 130 131 static const plat_psci_ops_t imx_plat_psci_ops = { 132 .pwr_domain_on = imx_pwr_domain_on, 133 .pwr_domain_on_finish = imx_pwr_domain_on_finish, 134 .pwr_domain_off = imx_pwr_domain_off, 135 .pwr_domain_suspend = imx_domain_suspend, 136 .pwr_domain_suspend_finish = imx_domain_suspend_finish, 137 .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, 138 .validate_power_state = imx_validate_power_state, 139 .validate_ns_entrypoint = imx_validate_ns_entrypoint, 140 .system_off = imx_system_off, 141 .system_reset = imx_system_reset, 142 }; 143 144 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 145 const plat_psci_ops_t **psci_ops) 146 { 147 imx_mailbox_init(sec_entrypoint); 148 *psci_ops = &imx_plat_psci_ops; 149 150 /* Request low power mode for cluster/cci, only need to do once */ 151 sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF); 152 sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_OFF); 153 sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF); 154 155 /* Request RUN and LP modes for DDR, system interconnect etc. */ 156 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, 157 SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 158 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, 159 SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 160 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, 161 SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 162 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, 163 SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 164 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, 165 SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, 166 SC_PM_PW_MODE_STBY); 167 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, 168 SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, 169 SC_PM_PW_MODE_STBY); 170 171 return 0; 172 } 173