1*baa7650bSAnson Huang /* 2*baa7650bSAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*baa7650bSAnson Huang * 4*baa7650bSAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*baa7650bSAnson Huang */ 6*baa7650bSAnson Huang 7*baa7650bSAnson Huang #include <arch.h> 8*baa7650bSAnson Huang #include <arch_helpers.h> 9*baa7650bSAnson Huang #include <cci.h> 10*baa7650bSAnson Huang #include <debug.h> 11*baa7650bSAnson Huang #include <gicv3.h> 12*baa7650bSAnson Huang #include <mmio.h> 13*baa7650bSAnson Huang #include <plat_imx8.h> 14*baa7650bSAnson Huang #include <psci.h> 15*baa7650bSAnson Huang #include <sci/sci.h> 16*baa7650bSAnson Huang #include <stdbool.h> 17*baa7650bSAnson Huang 18*baa7650bSAnson Huang const static int ap_core_index[PLATFORM_CORE_COUNT] = { 19*baa7650bSAnson Huang SC_R_A53_0, SC_R_A53_1, SC_R_A53_2, 20*baa7650bSAnson Huang SC_R_A53_3, SC_R_A72_0, SC_R_A72_1, 21*baa7650bSAnson Huang }; 22*baa7650bSAnson Huang 23*baa7650bSAnson Huang /* need to enable USE_COHERENT_MEM to avoid coherence issue */ 24*baa7650bSAnson Huang #if USE_COHERENT_MEM 25*baa7650bSAnson Huang static unsigned int a53_cpu_on_number __section("tzfw_coherent_mem"); 26*baa7650bSAnson Huang static unsigned int a72_cpu_on_number __section("tzfw_coherent_mem"); 27*baa7650bSAnson Huang #endif 28*baa7650bSAnson Huang 29*baa7650bSAnson Huang int imx_pwr_domain_on(u_register_t mpidr) 30*baa7650bSAnson Huang { 31*baa7650bSAnson Huang int ret = PSCI_E_SUCCESS; 32*baa7650bSAnson Huang unsigned int cluster_id, cpu_id; 33*baa7650bSAnson Huang 34*baa7650bSAnson Huang cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 35*baa7650bSAnson Huang cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 36*baa7650bSAnson Huang 37*baa7650bSAnson Huang tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id); 38*baa7650bSAnson Huang 39*baa7650bSAnson Huang if (cluster_id == 0) { 40*baa7650bSAnson Huang if (a53_cpu_on_number == 0) 41*baa7650bSAnson Huang sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON); 42*baa7650bSAnson Huang 43*baa7650bSAnson Huang if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 44*baa7650bSAnson Huang SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 45*baa7650bSAnson Huang ERROR("cluster0 core %d power on failed!\n", cpu_id); 46*baa7650bSAnson Huang ret = PSCI_E_INTERN_FAIL; 47*baa7650bSAnson Huang } 48*baa7650bSAnson Huang 49*baa7650bSAnson Huang if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 50*baa7650bSAnson Huang true, BL31_BASE) != SC_ERR_NONE) { 51*baa7650bSAnson Huang ERROR("boot cluster0 core %d failed!\n", cpu_id); 52*baa7650bSAnson Huang ret = PSCI_E_INTERN_FAIL; 53*baa7650bSAnson Huang } 54*baa7650bSAnson Huang } else { 55*baa7650bSAnson Huang if (a72_cpu_on_number == 0) 56*baa7650bSAnson Huang sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); 57*baa7650bSAnson Huang 58*baa7650bSAnson Huang if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id + 4], 59*baa7650bSAnson Huang SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 60*baa7650bSAnson Huang ERROR(" cluster1 core %d power on failed!\n", cpu_id); 61*baa7650bSAnson Huang ret = PSCI_E_INTERN_FAIL; 62*baa7650bSAnson Huang } 63*baa7650bSAnson Huang 64*baa7650bSAnson Huang if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id + 4], 65*baa7650bSAnson Huang true, BL31_BASE) != SC_ERR_NONE) { 66*baa7650bSAnson Huang ERROR("boot cluster1 core %d failed!\n", cpu_id); 67*baa7650bSAnson Huang ret = PSCI_E_INTERN_FAIL; 68*baa7650bSAnson Huang } 69*baa7650bSAnson Huang } 70*baa7650bSAnson Huang 71*baa7650bSAnson Huang return ret; 72*baa7650bSAnson Huang } 73*baa7650bSAnson Huang 74*baa7650bSAnson Huang void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 75*baa7650bSAnson Huang { 76*baa7650bSAnson Huang uint64_t mpidr = read_mpidr_el1(); 77*baa7650bSAnson Huang unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 78*baa7650bSAnson Huang 79*baa7650bSAnson Huang if (cluster_id == 0 && a53_cpu_on_number++ == 0) 80*baa7650bSAnson Huang cci_enable_snoop_dvm_reqs(0); 81*baa7650bSAnson Huang if (cluster_id == 1 && a72_cpu_on_number++ == 0) 82*baa7650bSAnson Huang cci_enable_snoop_dvm_reqs(1); 83*baa7650bSAnson Huang 84*baa7650bSAnson Huang plat_gic_pcpu_init(); 85*baa7650bSAnson Huang plat_gic_cpuif_enable(); 86*baa7650bSAnson Huang } 87*baa7650bSAnson Huang 88*baa7650bSAnson Huang int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 89*baa7650bSAnson Huang { 90*baa7650bSAnson Huang return PSCI_E_SUCCESS; 91*baa7650bSAnson Huang } 92*baa7650bSAnson Huang 93*baa7650bSAnson Huang static const plat_psci_ops_t imx_plat_psci_ops = { 94*baa7650bSAnson Huang .pwr_domain_on = imx_pwr_domain_on, 95*baa7650bSAnson Huang .pwr_domain_on_finish = imx_pwr_domain_on_finish, 96*baa7650bSAnson Huang .validate_ns_entrypoint = imx_validate_ns_entrypoint, 97*baa7650bSAnson Huang }; 98*baa7650bSAnson Huang 99*baa7650bSAnson Huang int plat_setup_psci_ops(uintptr_t sec_entrypoint, 100*baa7650bSAnson Huang const plat_psci_ops_t **psci_ops) 101*baa7650bSAnson Huang { 102*baa7650bSAnson Huang uint64_t mpidr = read_mpidr_el1(); 103*baa7650bSAnson Huang unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 104*baa7650bSAnson Huang 105*baa7650bSAnson Huang imx_mailbox_init(sec_entrypoint); 106*baa7650bSAnson Huang *psci_ops = &imx_plat_psci_ops; 107*baa7650bSAnson Huang 108*baa7650bSAnson Huang if (cluster_id == 0) 109*baa7650bSAnson Huang a53_cpu_on_number++; 110*baa7650bSAnson Huang else 111*baa7650bSAnson Huang a72_cpu_on_number++; 112*baa7650bSAnson Huang 113*baa7650bSAnson Huang return 0; 114*baa7650bSAnson Huang } 115