1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <context.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/console.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <plat/common/platform.h> 22 23 #include <imx8qm_pads.h> 24 #include <imx8_iomux.h> 25 #include <imx8_lpuart.h> 26 #include <plat_imx8.h> 27 #include <sci/sci.h> 28 #include <sec_rsrc.h> 29 30 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 31 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 32 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); 33 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); 34 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 35 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 36 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \ 41 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ 42 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ 43 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ 44 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) 45 46 const static int imx8qm_cci_map[] = { 47 CLUSTER0_CCI_SLVAE_IFACE, 48 CLUSTER1_CCI_SLVAE_IFACE 49 }; 50 51 static const mmap_region_t imx_mmap[] = { 52 MAP_REGION_FLAT(IMX_BOOT_UART_BASE, IMX_BOOT_UART_SIZE, MT_DEVICE | MT_RW), 53 MAP_REGION_FLAT(SC_IPC_BASE, SC_IPC_SIZE, MT_DEVICE | MT_RW), 54 MAP_REGION_FLAT(PLAT_GICD_BASE, PLAT_GICD_SIZE, MT_DEVICE | MT_RW), 55 MAP_REGION_FLAT(PLAT_GICR_BASE, PLAT_GICR_SIZE, MT_DEVICE | MT_RW), 56 MAP_REGION_FLAT(PLAT_CCI_BASE, PLAT_CCI_SIZE, MT_DEVICE | MT_RW), 57 {0} 58 }; 59 60 static uint32_t get_spsr_for_bl33_entry(void) 61 { 62 unsigned long el_status; 63 unsigned long mode; 64 uint32_t spsr; 65 66 /* figure out what mode we enter the non-secure world */ 67 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 68 el_status &= ID_AA64PFR0_ELX_MASK; 69 70 mode = (el_status) ? MODE_EL2 : MODE_EL1; 71 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 72 73 return spsr; 74 } 75 76 #if DEBUG_CONSOLE_A53 77 static void lpuart32_serial_setbrg(unsigned int base, int baudrate) 78 { 79 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr; 80 unsigned int diff1, diff2, tmp, rate; 81 82 if (baudrate == 0) 83 panic(); 84 85 sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 86 87 baud_diff = baudrate; 88 osr = 0; 89 sbr = 0; 90 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 91 tmp_sbr = (rate / (baudrate * tmp_osr)); 92 if (tmp_sbr == 0) 93 tmp_sbr = 1; 94 95 /* calculate difference in actual baud w/ current values */ 96 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; 97 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); 98 99 /* select best values between sbr and sbr+1 */ 100 if (diff1 > (baudrate - diff2)) { 101 diff1 = baudrate - diff2; 102 tmp_sbr++; 103 } 104 105 if (diff1 <= baud_diff) { 106 baud_diff = diff1; 107 osr = tmp_osr; 108 sbr = tmp_sbr; 109 } 110 } 111 112 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); 113 114 if ((osr > 3) && (osr < 8)) 115 tmp |= LPUART_BAUD_BOTHEDGE_MASK; 116 117 tmp &= ~LPUART_BAUD_OSR_MASK; 118 tmp |= LPUART_BAUD_OSR(osr - 1); 119 tmp &= ~LPUART_BAUD_SBR_MASK; 120 tmp |= LPUART_BAUD_SBR(sbr); 121 122 /* explicitly disable 10 bit mode & set 1 stop bit */ 123 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); 124 125 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); 126 } 127 128 static int lpuart32_serial_init(unsigned int base) 129 { 130 unsigned int tmp; 131 132 /* disable TX & RX before enabling clocks */ 133 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 134 tmp &= ~(CTRL_TE | CTRL_RE); 135 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 136 137 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); 138 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); 139 140 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); 141 142 /* provide data bits, parity, stop bit, etc */ 143 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); 144 145 /* eight data bits no parity bit */ 146 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 147 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); 148 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 149 150 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE); 151 152 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 153 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 154 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); 155 156 return 0; 157 } 158 #endif 159 160 void mx8_partition_resources(void) 161 { 162 sc_rm_pt_t secure_part, os_part; 163 sc_rm_mr_t mr, mr_record = 64; 164 sc_faddr_t start, end; 165 bool owned, owned2; 166 sc_err_t err; 167 int i; 168 169 err = sc_rm_get_partition(ipc_handle, &secure_part); 170 171 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false, 172 false, false, false); 173 174 err = sc_rm_set_parent(ipc_handle, os_part, secure_part); 175 176 /* set secure resources to NOT-movable */ 177 for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) { 178 err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i], 179 secure_rsrcs[i], false); 180 if (err) 181 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 182 secure_rsrcs[i], err); 183 } 184 185 owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0); 186 if (owned) { 187 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, 188 SC_R_M4_0_PID0, false); 189 if (err) 190 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 191 SC_R_M4_0_PID0, err); 192 } 193 194 owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0); 195 if (owned2) { 196 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, 197 SC_R_M4_1_PID0, false); 198 if (err) 199 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 200 SC_R_M4_1_PID0, err); 201 } 202 /* move all movable resources and pins to non-secure partition */ 203 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true); 204 if (err) 205 ERROR("sc_rm_move_all: %u\n", err); 206 207 /* iterate through peripherals to give NS OS part access */ 208 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { 209 err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i], 210 os_part, SC_RM_PERM_FULL); 211 if (err) 212 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \ 213 ret %u\n", ns_access_allowed[i], err); 214 } 215 216 if (owned) { 217 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, 218 SC_R_M4_0_PID0, true); 219 if (err) 220 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 221 SC_R_M4_0_PID0, err); 222 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0); 223 if (err) 224 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", 225 SC_R_M4_0_PID0, err); 226 } 227 if (owned2) { 228 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, 229 SC_R_M4_1_PID0, true); 230 if (err) 231 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 232 SC_R_M4_1_PID0, err); 233 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0); 234 if (err) 235 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", 236 SC_R_M4_1_PID0, err); 237 } 238 239 /* 240 * sc_rm_set_peripheral_permissions 241 * sc_rm_set_memreg_permissions 242 * sc_rm_set_pin_movable 243 */ 244 245 for (mr = 0; mr < 64; mr++) { 246 owned = sc_rm_is_memreg_owned(ipc_handle, mr); 247 if (owned) { 248 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end); 249 if (err) 250 ERROR("Memreg get info failed, %u\n", mr); 251 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end); 252 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { 253 mr_record = mr; /* Record the mr for ATF running */ 254 } else { 255 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 256 if (err) 257 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \ 258 err %d\n", start, end, err); 259 } 260 } 261 } 262 263 if (mr_record != 64) { 264 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end); 265 if (err) 266 ERROR("Memreg get info failed, %u\n", mr_record); 267 if ((BL31_LIMIT - 1) < end) { 268 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); 269 if (err) 270 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 271 (sc_faddr_t)BL31_LIMIT, end); 272 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 273 if (err) 274 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 275 (sc_faddr_t)BL31_LIMIT, end); 276 } 277 278 if (start < (BL31_BASE - 1)) { 279 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1); 280 if (err) 281 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 282 start, (sc_faddr_t)BL31_BASE - 1); 283 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 284 if (err) 285 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 286 start, (sc_faddr_t)BL31_BASE - 1); 287 } 288 } 289 290 if (err) 291 NOTICE("Partitioning Failed\n"); 292 else 293 NOTICE("Non-secure Partitioning Succeeded\n"); 294 295 } 296 297 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 298 u_register_t arg2, u_register_t arg3) 299 { 300 #if DEBUG_CONSOLE 301 static console_lpuart_t console; 302 #endif 303 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) 304 panic(); 305 306 #if DEBUG_CONSOLE_A53 307 sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); 308 sc_pm_clock_rate_t rate = 80000000; 309 sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 310 sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); 311 312 /* configure UART pads */ 313 sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); 314 sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); 315 sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL); 316 sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL); 317 lpuart32_serial_init(IMX_BOOT_UART_BASE); 318 #endif 319 320 #if DEBUG_CONSOLE 321 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 322 IMX_CONSOLE_BAUDRATE, &console); 323 #endif 324 325 /* turn on MU1 for non-secure OS/Hypervisor */ 326 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); 327 328 /* 329 * create new partition for non-secure OS/Hypervisor 330 * uses global structs defined in sec_rsrc.h 331 */ 332 mx8_partition_resources(); 333 334 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 335 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 336 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 337 338 /* init the first cluster's cci slave interface */ 339 cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT); 340 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 341 } 342 343 void bl31_plat_arch_setup(void) 344 { 345 unsigned long ro_start = BL31_RO_START; 346 unsigned long ro_size = BL31_RO_END - BL31_RO_START; 347 unsigned long rw_start = BL31_RW_START; 348 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 349 #if USE_COHERENT_MEM 350 unsigned long coh_start = BL31_COHERENT_RAM_START; 351 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START; 352 #endif 353 354 mmap_add_region(ro_start, ro_start, ro_size, 355 MT_RO | MT_MEMORY | MT_SECURE); 356 mmap_add_region(rw_start, rw_start, rw_size, 357 MT_RW | MT_MEMORY | MT_SECURE); 358 mmap_add(imx_mmap); 359 360 #if USE_COHERENT_MEM 361 mmap_add_region(coh_start, coh_start, coh_size, 362 MT_DEVICE | MT_RW | MT_SECURE); 363 #endif 364 365 /* setup xlat table */ 366 init_xlat_tables(); 367 /* enable the MMU */ 368 enable_mmu_el3(0); 369 } 370 371 void bl31_platform_setup(void) 372 { 373 plat_gic_driver_init(); 374 plat_gic_init(); 375 } 376 377 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 378 { 379 if (type == NON_SECURE) 380 return &bl33_image_ep_info; 381 if (type == SECURE) 382 return &bl32_image_ep_info; 383 384 return NULL; 385 } 386 387 unsigned int plat_get_syscnt_freq2(void) 388 { 389 return COUNTER_FREQUENCY; 390 } 391 392 void bl31_plat_runtime_setup(void) 393 { 394 return; 395 } 396