1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <context.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/console.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <plat/common/platform.h> 22 23 #include <imx8qm_pads.h> 24 #include <imx8_iomux.h> 25 #include <imx8_lpuart.h> 26 #include <plat_imx8.h> 27 #include <sci/sci.h> 28 #include <sec_rsrc.h> 29 30 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 31 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 32 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); 33 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); 34 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 35 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 36 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \ 41 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ 42 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ 43 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ 44 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) 45 46 const static int imx8qm_cci_map[] = { 47 CLUSTER0_CCI_SLVAE_IFACE, 48 CLUSTER1_CCI_SLVAE_IFACE 49 }; 50 51 static const mmap_region_t imx_mmap[] = { 52 MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW), 53 {0} 54 }; 55 56 static uint32_t get_spsr_for_bl33_entry(void) 57 { 58 unsigned long el_status; 59 unsigned long mode; 60 uint32_t spsr; 61 62 /* figure out what mode we enter the non-secure world */ 63 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 64 el_status &= ID_AA64PFR0_ELX_MASK; 65 66 mode = (el_status) ? MODE_EL2 : MODE_EL1; 67 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 68 69 return spsr; 70 } 71 72 #if DEBUG_CONSOLE_A53 73 static void lpuart32_serial_setbrg(unsigned int base, int baudrate) 74 { 75 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr; 76 unsigned int diff1, diff2, tmp, rate; 77 78 if (baudrate == 0) 79 panic(); 80 81 sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 82 83 baud_diff = baudrate; 84 osr = 0; 85 sbr = 0; 86 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 87 tmp_sbr = (rate / (baudrate * tmp_osr)); 88 if (tmp_sbr == 0) 89 tmp_sbr = 1; 90 91 /* calculate difference in actual baud w/ current values */ 92 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; 93 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); 94 95 /* select best values between sbr and sbr+1 */ 96 if (diff1 > (baudrate - diff2)) { 97 diff1 = baudrate - diff2; 98 tmp_sbr++; 99 } 100 101 if (diff1 <= baud_diff) { 102 baud_diff = diff1; 103 osr = tmp_osr; 104 sbr = tmp_sbr; 105 } 106 } 107 108 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); 109 110 if ((osr > 3) && (osr < 8)) 111 tmp |= LPUART_BAUD_BOTHEDGE_MASK; 112 113 tmp &= ~LPUART_BAUD_OSR_MASK; 114 tmp |= LPUART_BAUD_OSR(osr - 1); 115 tmp &= ~LPUART_BAUD_SBR_MASK; 116 tmp |= LPUART_BAUD_SBR(sbr); 117 118 /* explicitly disable 10 bit mode & set 1 stop bit */ 119 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); 120 121 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); 122 } 123 124 static int lpuart32_serial_init(unsigned int base) 125 { 126 unsigned int tmp; 127 128 /* disable TX & RX before enabling clocks */ 129 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 130 tmp &= ~(CTRL_TE | CTRL_RE); 131 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 132 133 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); 134 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); 135 136 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); 137 138 /* provide data bits, parity, stop bit, etc */ 139 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); 140 141 /* eight data bits no parity bit */ 142 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 143 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); 144 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 145 146 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE); 147 148 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 149 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 150 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); 151 152 return 0; 153 } 154 #endif 155 156 void mx8_partition_resources(void) 157 { 158 sc_rm_pt_t secure_part, os_part; 159 sc_rm_mr_t mr, mr_record = 64; 160 sc_faddr_t start, end; 161 bool owned, owned2; 162 sc_err_t err; 163 int i; 164 165 err = sc_rm_get_partition(ipc_handle, &secure_part); 166 167 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false, 168 false, false, false); 169 170 err = sc_rm_set_parent(ipc_handle, os_part, secure_part); 171 172 /* set secure resources to NOT-movable */ 173 for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) { 174 err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i], 175 secure_rsrcs[i], false); 176 if (err) 177 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 178 secure_rsrcs[i], err); 179 } 180 181 owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0); 182 if (owned) { 183 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, 184 SC_R_M4_0_PID0, false); 185 if (err) 186 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 187 SC_R_M4_0_PID0, err); 188 } 189 190 owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0); 191 if (owned2) { 192 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, 193 SC_R_M4_1_PID0, false); 194 if (err) 195 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 196 SC_R_M4_1_PID0, err); 197 } 198 /* move all movable resources and pins to non-secure partition */ 199 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true); 200 if (err) 201 ERROR("sc_rm_move_all: %u\n", err); 202 203 /* iterate through peripherals to give NS OS part access */ 204 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { 205 err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i], 206 os_part, SC_RM_PERM_FULL); 207 if (err) 208 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \ 209 ret %u\n", ns_access_allowed[i], err); 210 } 211 212 if (owned) { 213 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, 214 SC_R_M4_0_PID0, true); 215 if (err) 216 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 217 SC_R_M4_0_PID0, err); 218 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0); 219 if (err) 220 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", 221 SC_R_M4_0_PID0, err); 222 } 223 if (owned2) { 224 err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, 225 SC_R_M4_1_PID0, true); 226 if (err) 227 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 228 SC_R_M4_1_PID0, err); 229 err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0); 230 if (err) 231 ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", 232 SC_R_M4_1_PID0, err); 233 } 234 235 /* 236 * sc_rm_set_peripheral_permissions 237 * sc_rm_set_memreg_permissions 238 * sc_rm_set_pin_movable 239 */ 240 241 for (mr = 0; mr < 64; mr++) { 242 owned = sc_rm_is_memreg_owned(ipc_handle, mr); 243 if (owned) { 244 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end); 245 if (err) 246 ERROR("Memreg get info failed, %u\n", mr); 247 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end); 248 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { 249 mr_record = mr; /* Record the mr for ATF running */ 250 } else { 251 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 252 if (err) 253 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \ 254 err %d\n", start, end, err); 255 } 256 } 257 } 258 259 if (mr_record != 64) { 260 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end); 261 if (err) 262 ERROR("Memreg get info failed, %u\n", mr_record); 263 if ((BL31_LIMIT - 1) < end) { 264 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); 265 if (err) 266 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 267 (sc_faddr_t)BL31_LIMIT, end); 268 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 269 if (err) 270 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 271 (sc_faddr_t)BL31_LIMIT, end); 272 } 273 274 if (start < (BL31_BASE - 1)) { 275 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1); 276 if (err) 277 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 278 start, (sc_faddr_t)BL31_BASE - 1); 279 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 280 if (err) 281 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 282 start, (sc_faddr_t)BL31_BASE - 1); 283 } 284 } 285 286 if (err) 287 NOTICE("Partitioning Failed\n"); 288 else 289 NOTICE("Non-secure Partitioning Succeeded\n"); 290 291 } 292 293 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 294 u_register_t arg2, u_register_t arg3) 295 { 296 #if DEBUG_CONSOLE 297 static console_lpuart_t console; 298 #endif 299 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) 300 panic(); 301 302 #if DEBUG_CONSOLE_A53 303 sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); 304 sc_pm_clock_rate_t rate = 80000000; 305 sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 306 sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); 307 308 /* configure UART pads */ 309 sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); 310 sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); 311 sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL); 312 sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL); 313 lpuart32_serial_init(IMX_BOOT_UART_BASE); 314 #endif 315 316 #if DEBUG_CONSOLE 317 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 318 IMX_CONSOLE_BAUDRATE, &console); 319 #endif 320 321 /* turn on MU1 for non-secure OS/Hypervisor */ 322 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); 323 /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */ 324 sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); 325 sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); 326 mmio_write_32(IMX_GPT_LPCG_BASE, mmio_read_32(IMX_GPT_LPCG_BASE) | (1 << 25)); 327 328 /* 329 * create new partition for non-secure OS/Hypervisor 330 * uses global structs defined in sec_rsrc.h 331 */ 332 mx8_partition_resources(); 333 334 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 335 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 336 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 337 338 /* init the first cluster's cci slave interface */ 339 cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT); 340 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 341 } 342 343 void bl31_plat_arch_setup(void) 344 { 345 unsigned long ro_start = BL31_RO_START; 346 unsigned long ro_size = BL31_RO_END - BL31_RO_START; 347 unsigned long rw_start = BL31_RW_START; 348 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 349 #if USE_COHERENT_MEM 350 unsigned long coh_start = BL31_COHERENT_RAM_START; 351 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START; 352 #endif 353 354 mmap_add_region(ro_start, ro_start, ro_size, 355 MT_RO | MT_MEMORY | MT_SECURE); 356 mmap_add_region(rw_start, rw_start, rw_size, 357 MT_RW | MT_MEMORY | MT_SECURE); 358 mmap_add(imx_mmap); 359 360 #if USE_COHERENT_MEM 361 mmap_add_region(coh_start, coh_start, coh_size, 362 MT_DEVICE | MT_RW | MT_SECURE); 363 #endif 364 365 /* setup xlat table */ 366 init_xlat_tables(); 367 /* enable the MMU */ 368 enable_mmu_el3(0); 369 } 370 371 void bl31_platform_setup(void) 372 { 373 plat_gic_driver_init(); 374 plat_gic_init(); 375 } 376 377 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 378 { 379 if (type == NON_SECURE) 380 return &bl33_image_ep_info; 381 if (type == SECURE) 382 return &bl32_image_ep_info; 383 384 return NULL; 385 } 386 387 unsigned int plat_get_syscnt_freq2(void) 388 { 389 return COUNTER_FREQUENCY; 390 } 391 392 void bl31_plat_runtime_setup(void) 393 { 394 return; 395 } 396