1*3d660799SJacky Bai /* 2*3d660799SJacky Bai * Copyright (c) 2019, NXP. All rights reserved. 3*3d660799SJacky Bai * 4*3d660799SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*3d660799SJacky Bai */ 6*3d660799SJacky Bai 7*3d660799SJacky Bai #ifndef IMX_RDC_H 8*3d660799SJacky Bai #define IMX_RDC_H 9*3d660799SJacky Bai 10*3d660799SJacky Bai #include <lib/utils_def.h> 11*3d660799SJacky Bai 12*3d660799SJacky Bai #include <platform_def.h> 13*3d660799SJacky Bai 14*3d660799SJacky Bai #define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4) 15*3d660799SJacky Bai #define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4) 16*3d660799SJacky Bai #define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 4) 17*3d660799SJacky Bai #define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 4) 18*3d660799SJacky Bai #define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 4) 19*3d660799SJacky Bai 20*3d660799SJacky Bai #define LCK BIT(31) 21*3d660799SJacky Bai #define SREQ BIT(30) 22*3d660799SJacky Bai #define ENA BIT(30) 23*3d660799SJacky Bai 24*3d660799SJacky Bai #define DID0 U(0x0) 25*3d660799SJacky Bai #define DID1 U(0x1) 26*3d660799SJacky Bai #define DID2 U(0x2) 27*3d660799SJacky Bai #define DID3 U(0x3) 28*3d660799SJacky Bai 29*3d660799SJacky Bai #define D3R BIT(7) 30*3d660799SJacky Bai #define D3W BIT(6) 31*3d660799SJacky Bai #define D2R BIT(5) 32*3d660799SJacky Bai #define D2W BIT(4) 33*3d660799SJacky Bai #define D1R BIT(3) 34*3d660799SJacky Bai #define D1W BIT(2) 35*3d660799SJacky Bai #define D0R BIT(1) 36*3d660799SJacky Bai #define D0W BIT(0) 37*3d660799SJacky Bai 38*3d660799SJacky Bai union rdc_setting { 39*3d660799SJacky Bai uint32_t rdc_mda; /* Master Domain Assignment */ 40*3d660799SJacky Bai uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */ 41*3d660799SJacky Bai uint32_t rdc_mem_region[3]; /* Memory Region Access Control */ 42*3d660799SJacky Bai }; 43*3d660799SJacky Bai 44*3d660799SJacky Bai enum rdc_type { 45*3d660799SJacky Bai RDC_INVALID, 46*3d660799SJacky Bai RDC_MDA, 47*3d660799SJacky Bai RDC_PDAP, 48*3d660799SJacky Bai RDC_MEM_REGION, 49*3d660799SJacky Bai }; 50*3d660799SJacky Bai 51*3d660799SJacky Bai struct imx_rdc_cfg { 52*3d660799SJacky Bai enum rdc_type type; /* config type Master, Peripheral or Memory region */ 53*3d660799SJacky Bai int index; 54*3d660799SJacky Bai union rdc_setting setting; 55*3d660799SJacky Bai }; 56*3d660799SJacky Bai 57*3d660799SJacky Bai #define RDC_MDAn(i, mda) \ 58*3d660799SJacky Bai {RDC_MDA, (i), .setting.rdc_mda = (mda), } 59*3d660799SJacky Bai #define RDC_PDAPn(i, pdap) \ 60*3d660799SJacky Bai {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), } 61*3d660799SJacky Bai 62*3d660799SJacky Bai #define RDC_MEM_REGIONn(i, msa, mea, mrc) \ 63*3d660799SJacky Bai { RDC_MEM_REGION, (i), \ 64*3d660799SJacky Bai .setting.rdc_mem_region[0] = (msa), \ 65*3d660799SJacky Bai .setting.rdc_mem_region[1] = (mea), \ 66*3d660799SJacky Bai .setting.rdc_mem_region[2] = (mrc), \ 67*3d660799SJacky Bai } 68*3d660799SJacky Bai 69*3d660799SJacky Bai void imx_rdc_init(const struct imx_rdc_cfg *cfg); 70*3d660799SJacky Bai 71*3d660799SJacky Bai #endif /* IMX_RDC_H */ 72*3d660799SJacky Bai 73