181136819SBai Ping /* 2e8837b0aSJacky Bai * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 381136819SBai Ping * 481136819SBai Ping * SPDX-License-Identifier: BSD-3-Clause 581136819SBai Ping */ 681136819SBai Ping 781136819SBai Ping #ifndef IMX8M_GPC_H 881136819SBai Ping #define IMX8M_GPC_H 981136819SBai Ping 109e5c3e92SJacky Bai #include <gpc_reg.h> 1158fdd608SJacky Bai 1281136819SBai Ping /* helper macro */ 1381136819SBai Ping #define A53_LPM_MASK U(0xF) 1481136819SBai Ping #define A53_LPM_WAIT U(0x5) 1581136819SBai Ping #define A53_LPM_STOP U(0xA) 16e8837b0aSJacky Bai #define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP) 1781136819SBai Ping 1881136819SBai Ping #define DSM_MODE_MASK BIT(31) 199e5c3e92SJacky Bai #define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3) 2081136819SBai Ping #define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2)) 2181136819SBai Ping #define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40) 2281136819SBai Ping #define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16)) 2381136819SBai Ping #define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20))) 2481136819SBai Ping #define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21))) 2581136819SBai Ping #define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4))) 2681136819SBai Ping #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) 2781136819SBai Ping 28e8837b0aSJacky Bai #define IMR_MASK_ALL 0xffffffff 29e8837b0aSJacky Bai 30a775ef25SJacky Bai #define IMX_PD_DOMAIN(name, on) \ 31a775ef25SJacky Bai { \ 32a775ef25SJacky Bai .pwr_req = name##_PWR_REQ, \ 33a775ef25SJacky Bai .pgc_offset = name##_PGC, \ 34a775ef25SJacky Bai .need_sync = false, \ 35a775ef25SJacky Bai .always_on = true, \ 36a775ef25SJacky Bai } 37a775ef25SJacky Bai 38a775ef25SJacky Bai #define IMX_MIX_DOMAIN(name, on) \ 39a775ef25SJacky Bai { \ 40a775ef25SJacky Bai .pwr_req = name##_PWR_REQ, \ 41a775ef25SJacky Bai .pgc_offset = name##_PGC, \ 42a775ef25SJacky Bai .adb400_sync = name##_ADB400_SYNC, \ 43a775ef25SJacky Bai .adb400_ack = name##_ADB400_ACK, \ 44a775ef25SJacky Bai .need_sync = true, \ 45a775ef25SJacky Bai .always_on = true, \ 46a775ef25SJacky Bai } 47a775ef25SJacky Bai 48a775ef25SJacky Bai struct imx_pwr_domain { 49a775ef25SJacky Bai uint32_t pwr_req; 50a775ef25SJacky Bai uint32_t adb400_sync; 51a775ef25SJacky Bai uint32_t adb400_ack; 52a775ef25SJacky Bai uint32_t pgc_offset; 53a775ef25SJacky Bai bool need_sync; 54a775ef25SJacky Bai bool always_on; 55a775ef25SJacky Bai }; 56a775ef25SJacky Bai 57*fe5e1c14SJacky Bai DECLARE_BAKERY_LOCK(gpc_lock); 58*fe5e1c14SJacky Bai 5981136819SBai Ping /* function declare */ 6081136819SBai Ping void imx_gpc_init(void); 6181136819SBai Ping void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint); 6281136819SBai Ping void imx_set_cpu_pwr_off(unsigned int core_index); 6381136819SBai Ping void imx_set_cpu_pwr_on(unsigned int core_index); 6481136819SBai Ping void imx_set_cpu_lpm(unsigned int core_index, bool pdn); 6581136819SBai Ping void imx_set_cluster_standby(bool retention); 6681136819SBai Ping void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state); 67e8837b0aSJacky Bai void imx_noc_slot_config(bool pdn); 68e8837b0aSJacky Bai void imx_set_sys_wakeup(unsigned int last_core, bool pdn); 69e8837b0aSJacky Bai void imx_set_sys_lpm(unsigned last_core, bool retention); 7081136819SBai Ping void imx_set_rbc_count(void); 7181136819SBai Ping void imx_clear_rbc_count(void); 7281136819SBai Ping 7381136819SBai Ping #endif /*IMX8M_GPC_H */ 74