1*c71793c6SJacky Bai /* 2*c71793c6SJacky Bai * Copyright 2019-2022 NXP 3*c71793c6SJacky Bai * 4*c71793c6SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*c71793c6SJacky Bai */ 6*c71793c6SJacky Bai 7*c71793c6SJacky Bai #ifndef DRAM_H 8*c71793c6SJacky Bai #define DRAM_H 9*c71793c6SJacky Bai 10*c71793c6SJacky Bai #include <assert.h> 11*c71793c6SJacky Bai 12*c71793c6SJacky Bai #include <arch_helpers.h> 13*c71793c6SJacky Bai #include <lib/utils_def.h> 14*c71793c6SJacky Bai 15*c71793c6SJacky Bai #include <ddrc.h> 16*c71793c6SJacky Bai #include <platform_def.h> 17*c71793c6SJacky Bai 18*c71793c6SJacky Bai #define DDRC_LPDDR4 BIT(5) 19*c71793c6SJacky Bai #define DDRC_DDR4 BIT(4) 20*c71793c6SJacky Bai #define DDRC_DDR3L BIT(0) 21*c71793c6SJacky Bai #define DDR_TYPE_MASK U(0x3f) 22*c71793c6SJacky Bai #define ACTIVE_RANK_MASK U(0x3) 23*c71793c6SJacky Bai 24*c71793c6SJacky Bai /* reg & config param */ 25*c71793c6SJacky Bai struct dram_cfg_param { 26*c71793c6SJacky Bai unsigned int reg; 27*c71793c6SJacky Bai unsigned int val; 28*c71793c6SJacky Bai }; 29*c71793c6SJacky Bai 30*c71793c6SJacky Bai struct dram_timing_info { 31*c71793c6SJacky Bai /* umctl2 config */ 32*c71793c6SJacky Bai struct dram_cfg_param *ddrc_cfg; 33*c71793c6SJacky Bai unsigned int ddrc_cfg_num; 34*c71793c6SJacky Bai /* ddrphy config */ 35*c71793c6SJacky Bai struct dram_cfg_param *ddrphy_cfg; 36*c71793c6SJacky Bai unsigned int ddrphy_cfg_num; 37*c71793c6SJacky Bai /* ddr fsp train info */ 38*c71793c6SJacky Bai struct dram_fsp_msg *fsp_msg; 39*c71793c6SJacky Bai unsigned int fsp_msg_num; 40*c71793c6SJacky Bai /* ddr phy trained CSR */ 41*c71793c6SJacky Bai struct dram_cfg_param *ddrphy_trained_csr; 42*c71793c6SJacky Bai unsigned int ddrphy_trained_csr_num; 43*c71793c6SJacky Bai /* ddr phy PIE */ 44*c71793c6SJacky Bai struct dram_cfg_param *ddrphy_pie; 45*c71793c6SJacky Bai unsigned int ddrphy_pie_num; 46*c71793c6SJacky Bai /* initialized fsp table */ 47*c71793c6SJacky Bai unsigned int fsp_table[4]; 48*c71793c6SJacky Bai }; 49*c71793c6SJacky Bai 50*c71793c6SJacky Bai struct dram_info { 51*c71793c6SJacky Bai int dram_type; 52*c71793c6SJacky Bai unsigned int num_rank; 53*c71793c6SJacky Bai int current_fsp; 54*c71793c6SJacky Bai int boot_fsp; 55*c71793c6SJacky Bai struct dram_timing_info *timing_info; 56*c71793c6SJacky Bai }; 57*c71793c6SJacky Bai 58*c71793c6SJacky Bai extern struct dram_info dram_info; 59*c71793c6SJacky Bai 60*c71793c6SJacky Bai void dram_info_init(unsigned long dram_timing_base); 61*c71793c6SJacky Bai void dram_umctl2_init(struct dram_timing_info *timing); 62*c71793c6SJacky Bai void dram_phy_init(struct dram_timing_info *timing); 63*c71793c6SJacky Bai 64*c71793c6SJacky Bai /* dram retention */ 65*c71793c6SJacky Bai void dram_enter_retention(void); 66*c71793c6SJacky Bai void dram_exit_retention(void); 67*c71793c6SJacky Bai 68*c71793c6SJacky Bai #endif /* DRAM_H */ 69