1c71793c6SJacky Bai /* 2c71793c6SJacky Bai * Copyright 2019-2022 NXP 3c71793c6SJacky Bai * 4c71793c6SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5c71793c6SJacky Bai */ 6c71793c6SJacky Bai 7c71793c6SJacky Bai #ifndef DRAM_H 8c71793c6SJacky Bai #define DRAM_H 9c71793c6SJacky Bai 10c71793c6SJacky Bai #include <assert.h> 11c71793c6SJacky Bai 12c71793c6SJacky Bai #include <arch_helpers.h> 13c71793c6SJacky Bai #include <lib/utils_def.h> 14c71793c6SJacky Bai 15c71793c6SJacky Bai #include <ddrc.h> 16c71793c6SJacky Bai #include <platform_def.h> 17c71793c6SJacky Bai 18c71793c6SJacky Bai #define DDRC_LPDDR4 BIT(5) 19c71793c6SJacky Bai #define DDRC_DDR4 BIT(4) 20c71793c6SJacky Bai #define DDRC_DDR3L BIT(0) 21c71793c6SJacky Bai #define DDR_TYPE_MASK U(0x3f) 22c71793c6SJacky Bai #define ACTIVE_RANK_MASK U(0x3) 23c71793c6SJacky Bai 24c71793c6SJacky Bai /* reg & config param */ 25c71793c6SJacky Bai struct dram_cfg_param { 26c71793c6SJacky Bai unsigned int reg; 27c71793c6SJacky Bai unsigned int val; 28c71793c6SJacky Bai }; 29c71793c6SJacky Bai 30c71793c6SJacky Bai struct dram_timing_info { 31c71793c6SJacky Bai /* umctl2 config */ 32c71793c6SJacky Bai struct dram_cfg_param *ddrc_cfg; 33c71793c6SJacky Bai unsigned int ddrc_cfg_num; 34c71793c6SJacky Bai /* ddrphy config */ 35c71793c6SJacky Bai struct dram_cfg_param *ddrphy_cfg; 36c71793c6SJacky Bai unsigned int ddrphy_cfg_num; 37c71793c6SJacky Bai /* ddr fsp train info */ 38c71793c6SJacky Bai struct dram_fsp_msg *fsp_msg; 39c71793c6SJacky Bai unsigned int fsp_msg_num; 40c71793c6SJacky Bai /* ddr phy trained CSR */ 41c71793c6SJacky Bai struct dram_cfg_param *ddrphy_trained_csr; 42c71793c6SJacky Bai unsigned int ddrphy_trained_csr_num; 43c71793c6SJacky Bai /* ddr phy PIE */ 44c71793c6SJacky Bai struct dram_cfg_param *ddrphy_pie; 45c71793c6SJacky Bai unsigned int ddrphy_pie_num; 46c71793c6SJacky Bai /* initialized fsp table */ 47c71793c6SJacky Bai unsigned int fsp_table[4]; 48c71793c6SJacky Bai }; 49c71793c6SJacky Bai 50c71793c6SJacky Bai struct dram_info { 51c71793c6SJacky Bai int dram_type; 52c71793c6SJacky Bai unsigned int num_rank; 53*9c336f61SJacky Bai uint32_t num_fsp; 54c71793c6SJacky Bai int current_fsp; 55c71793c6SJacky Bai int boot_fsp; 56*9c336f61SJacky Bai bool bypass_mode; 57c71793c6SJacky Bai struct dram_timing_info *timing_info; 58*9c336f61SJacky Bai /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */ 59*9c336f61SJacky Bai uint32_t mr_table[3][8]; 60c71793c6SJacky Bai }; 61c71793c6SJacky Bai 62c71793c6SJacky Bai extern struct dram_info dram_info; 63c71793c6SJacky Bai 64c71793c6SJacky Bai void dram_info_init(unsigned long dram_timing_base); 65c71793c6SJacky Bai void dram_umctl2_init(struct dram_timing_info *timing); 66c71793c6SJacky Bai void dram_phy_init(struct dram_timing_info *timing); 67c71793c6SJacky Bai 68c71793c6SJacky Bai /* dram retention */ 69c71793c6SJacky Bai void dram_enter_retention(void); 70c71793c6SJacky Bai void dram_exit_retention(void); 71c71793c6SJacky Bai 72*9c336f61SJacky Bai void dram_clock_switch(unsigned int target_drate, bool bypass_mode); 73*9c336f61SJacky Bai 74*9c336f61SJacky Bai /* dram frequency change */ 75*9c336f61SJacky Bai void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index); 76*9c336f61SJacky Bai void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate); 77*9c336f61SJacky Bai 78c71793c6SJacky Bai #endif /* DRAM_H */ 79