1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 8 #define PLATFORM_LINKER_ARCH aarch64 9 10 #define PLATFORM_STACK_SIZE 0x800 11 #define CACHE_WRITEBACK_GRANULE 64 12 13 #define PLAT_PRIMARY_CPU 0x0 14 #define PLATFORM_MAX_CPU_PER_CLUSTER 4 15 #define PLATFORM_CLUSTER_COUNT 1 16 #define PLATFORM_CLUSTER0_CORE_COUNT 4 17 #define PLATFORM_CLUSTER1_CORE_COUNT 0 18 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 19 20 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 21 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 22 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 23 24 #define PWR_DOMAIN_AT_MAX_LVL U(1) 25 #define PLAT_MAX_PWR_LVL U(2) 26 #define PLAT_MAX_OFF_STATE U(4) 27 #define PLAT_MAX_RET_STATE U(1) 28 29 #define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE 30 #define PLAT_WAIT_OFF_STATE U(2) 31 #define PLAT_STOP_OFF_STATE U(3) 32 33 #define BL31_BASE U(0x910000) 34 #define BL31_LIMIT U(0x920000) 35 #define BL32_BASE U(0xfe000000) 36 37 /* non-secure uboot base */ 38 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 39 40 /* GICv3 base address */ 41 #define PLAT_GICD_BASE U(0x38800000) 42 #define PLAT_GICR_BASE U(0x38880000) 43 44 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 45 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 46 47 #define MAX_XLAT_TABLES 4 48 #define MAX_MMAP_REGIONS 14 49 50 #define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */ 51 52 #define IMX_BOOT_UART_BASE U(0x30860000) 53 #define IMX_BOOT_UART_CLK_IN_HZ 25000000 /* Select 25Mhz oscillator */ 54 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 55 #define PLAT_CRASH_UART_CLK_IN_HZ 25000000 56 #define IMX_CONSOLE_BAUDRATE 115200 57 58 #define IMX_AIPS_BASE U(0x30200000) 59 #define IMX_AIPS_SIZE U(0xC00000) 60 #define IMX_AIPS1_BASE U(0x30200000) 61 #define IMX_AIPS3_ARB_BASE U(0x30800000) 62 #define IMX_OCOTP_BASE U(0x30350000) 63 #define IMX_ANAMIX_BASE U(0x30360000) 64 #define IMX_CCM_BASE U(0x30380000) 65 #define IMX_SRC_BASE U(0x30390000) 66 #define IMX_GPC_BASE U(0x303a0000) 67 #define IMX_RDC_BASE U(0x303d0000) 68 #define IMX_CSU_BASE U(0x303e0000) 69 #define IMX_WDOG_BASE U(0x30280000) 70 #define IMX_SNVS_BASE U(0x30370000) 71 #define IMX_NOC_BASE U(0x32700000) 72 #define IMX_TZASC_BASE U(0x32F80000) 73 #define IMX_CAAM_BASE U(0x30900000) 74 #define IMX_IOMUX_GPR_BASE U(0x30340000) 75 #define IMX_DDRC_BASE U(0x3d400000) 76 #define IMX_DDRPHY_BASE U(0x3c000000) 77 #define IMX_DDR_IPS_BASE U(0x3d000000) 78 79 #define IMX_ROM_BASE U(0x00000000) 80 #define IMX_ROM_SIZE U(0x20000) 81 82 #define AIPSTZ1_BASE U(0x301f0000) 83 #define AIPSTZ2_BASE U(0x305f0000) 84 #define AIPSTZ3_BASE U(0x309f0000) 85 #define AIPSTZ4_BASE U(0x32df0000) 86 87 #define GPV_BASE U(0x32000000) 88 #define GPV_SIZE U(0x800000) 89 #define IMX_GIC_BASE PLAT_GICD_BASE 90 #define IMX_GIC_SIZE U(0x200000) 91 92 #define WDOG_WSR U(0x2) 93 #define WDOG_WCR_WDZST BIT(0) 94 #define WDOG_WCR_WDBG BIT(1) 95 #define WDOG_WCR_WDE BIT(2) 96 #define WDOG_WCR_WDT BIT(3) 97 #define WDOG_WCR_SRS BIT(4) 98 #define WDOG_WCR_WDA BIT(5) 99 #define WDOG_WCR_SRE BIT(6) 100 #define WDOG_WCR_WDW BIT(7) 101 102 #define SRC_A53RCR0 U(0x4) 103 #define SRC_A53RCR1 U(0x8) 104 #define SRC_OTG1PHY_SCR U(0x20) 105 #define SRC_OTG2PHY_SCR U(0x24) 106 #define SRC_GPR1_OFFSET U(0x74) 107 108 #define SNVS_LPCR U(0x38) 109 #define SNVS_LPCR_SRTC_ENV BIT(0) 110 #define SNVS_LPCR_DP_EN BIT(5) 111 #define SNVS_LPCR_TOP BIT(6) 112 113 114 #define IOMUXC_GPR10 U(0x28) 115 #define GPR_TZASC_EN BIT(0) 116 #define GPR_TZASC_EN_LOCK BIT(16) 117 118 #define OCRAM_S_BASE U(0x00180000) 119 #define OCRAM_S_SIZE U(0x8000) 120 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 121 122 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 123 124 #define DEBUG_CONSOLE 0 125 #define IMX_WDOG_B_RESET 126