1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_uart.h> 26 #include <plat_imx8.h> 27 28 IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 29 IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 30 IMPORT_SYM(uintptr_t, __RO_START__, BL31_RO_START); 31 IMPORT_SYM(uintptr_t, __RO_END__, BL31_RO_END); 32 IMPORT_SYM(uintptr_t, __RW_START__, BL31_RW_START); 33 IMPORT_SYM(uintptr_t, __RW_END__, BL31_RW_END); 34 35 static const mmap_region_t imx_mmap[] = { 36 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 37 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 38 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 39 {0}, 40 }; 41 42 static entry_point_info_t bl32_image_ep_info; 43 static entry_point_info_t bl33_image_ep_info; 44 45 /* get SPSR for BL33 entry */ 46 static uint32_t get_spsr_for_bl33_entry(void) 47 { 48 unsigned long el_status; 49 unsigned long mode; 50 uint32_t spsr; 51 52 /* figure out what mode we enter the non-secure world */ 53 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 54 el_status &= ID_AA64PFR0_ELX_MASK; 55 56 mode = (el_status) ? MODE_EL2 : MODE_EL1; 57 58 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 59 return spsr; 60 } 61 62 static void bl31_tz380_setup(void) 63 { 64 unsigned int val; 65 66 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 67 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 68 return; 69 70 tzc380_init(IMX_TZASC_BASE); 71 /* 72 * Need to substact offset 0x40000000 from CPU address when 73 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 74 */ 75 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 76 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 77 } 78 79 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 80 u_register_t arg2, u_register_t arg3) 81 { 82 int i; 83 /* enable CSU NS access permission */ 84 for (i = 0; i < 64; i++) { 85 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 86 } 87 88 /* config CAAM JRaMID set MID to Cortex A */ 89 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 90 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 91 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 92 93 #if DEBUG_CONSOLE 94 static console_uart_t console; 95 96 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 97 IMX_CONSOLE_BAUDRATE, &console); 98 #endif 99 /* 100 * tell BL3-1 where the non-secure software image is located 101 * and the entry state information. 102 */ 103 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 104 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 105 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 106 107 bl31_tz380_setup(); 108 } 109 110 void bl31_plat_arch_setup(void) 111 { 112 mmap_add_region(BL31_RO_START, BL31_RO_START, (BL31_RO_END - BL31_RO_START), 113 MT_MEMORY | MT_RO | MT_SECURE); 114 mmap_add_region(BL31_RW_START, BL31_RW_START, (BL31_RW_END - BL31_RW_START), 115 MT_MEMORY | MT_RW | MT_SECURE); 116 117 mmap_add(imx_mmap); 118 119 #if USE_COHERENT_MEM 120 mmap_add_region(BL31_COHERENT_RAM_START, BL31_COHERENT_RAM_START, 121 BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START, 122 MT_DEVICE | MT_RW | MT_SECURE); 123 #endif 124 /* setup xlat table */ 125 init_xlat_tables(); 126 /* enable the MMU */ 127 enable_mmu_el3(0); 128 } 129 130 void bl31_platform_setup(void) 131 { 132 generic_delay_timer_init(); 133 134 /* init the GICv3 cpu and distributor interface */ 135 plat_gic_driver_init(); 136 plat_gic_init(); 137 138 /* gpc init */ 139 imx_gpc_init(); 140 } 141 142 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 143 { 144 if (type == NON_SECURE) 145 return &bl33_image_ep_info; 146 if (type == SECURE) 147 return &bl32_image_ep_info; 148 149 return NULL; 150 } 151 152 unsigned int plat_get_syscnt_freq2(void) 153 { 154 return COUNTER_FREQUENCY; 155 } 156 157 void bl31_plat_runtime_setup(void) 158 { 159 return; 160 } 161