1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <imx8m_caam.h> 28 #include <plat_imx8.h> 29 30 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 31 32 static const mmap_region_t imx_mmap[] = { 33 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 34 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 35 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 36 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 37 {0}, 38 }; 39 40 static const struct aipstz_cfg aipstz[] = { 41 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {0}, 46 }; 47 48 static entry_point_info_t bl32_image_ep_info; 49 static entry_point_info_t bl33_image_ep_info; 50 51 static uint32_t imx_soc_revision; 52 53 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 54 u_register_t x3) 55 { 56 return imx_soc_revision; 57 } 58 59 #define ANAMIX_DIGPROG 0x6c 60 #define ROM_SOC_INFO_A0 0x800 61 #define ROM_SOC_INFO_B0 0x83C 62 #define OCOTP_SOC_INFO_B1 0x40 63 64 static void imx8mq_soc_info_init(void) 65 { 66 uint32_t rom_version; 67 uint32_t ocotp_val; 68 69 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 70 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 71 if (rom_version == 0x10) 72 return; 73 74 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 75 if (rom_version == 0x20) { 76 imx_soc_revision &= ~0xff; 77 imx_soc_revision |= rom_version; 78 return; 79 } 80 81 /* 0xff0055aa is magic number for B1 */ 82 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 83 if (ocotp_val == 0xff0055aa) { 84 imx_soc_revision &= ~0xff; 85 imx_soc_revision |= 0x21; 86 return; 87 } 88 } 89 90 /* get SPSR for BL33 entry */ 91 static uint32_t get_spsr_for_bl33_entry(void) 92 { 93 unsigned long el_status; 94 unsigned long mode; 95 uint32_t spsr; 96 97 /* figure out what mode we enter the non-secure world */ 98 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 99 el_status &= ID_AA64PFR0_ELX_MASK; 100 101 mode = (el_status) ? MODE_EL2 : MODE_EL1; 102 103 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 104 return spsr; 105 } 106 107 static void bl31_tz380_setup(void) 108 { 109 unsigned int val; 110 111 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 112 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 113 return; 114 115 tzc380_init(IMX_TZASC_BASE); 116 /* 117 * Need to substact offset 0x40000000 from CPU address when 118 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 119 */ 120 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 121 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 122 } 123 124 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 125 u_register_t arg2, u_register_t arg3) 126 { 127 int i; 128 /* enable CSU NS access permission */ 129 for (i = 0; i < 64; i++) { 130 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 131 } 132 133 imx_aipstz_init(aipstz); 134 135 #if DEBUG_CONSOLE 136 static console_t console; 137 138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 139 IMX_CONSOLE_BAUDRATE, &console); 140 #endif 141 142 imx8m_caam_init(); 143 144 /* 145 * tell BL3-1 where the non-secure software image is located 146 * and the entry state information. 147 */ 148 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 149 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 150 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 151 152 #if defined(SPD_opteed) || defined(SPD_trusty) 153 /* Populate entry point information for BL32 */ 154 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 155 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 156 bl32_image_ep_info.pc = BL32_BASE; 157 bl32_image_ep_info.spsr = 0; 158 159 /* Pass TEE base and size to bl33 */ 160 bl33_image_ep_info.args.arg1 = BL32_BASE; 161 bl33_image_ep_info.args.arg2 = BL32_SIZE; 162 163 #ifdef SPD_trusty 164 bl32_image_ep_info.args.arg0 = BL32_SIZE; 165 bl32_image_ep_info.args.arg1 = BL32_BASE; 166 #else 167 /* Make sure memory is clean */ 168 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 169 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 170 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 171 #endif 172 #endif 173 174 bl31_tz380_setup(); 175 } 176 177 void bl31_plat_arch_setup(void) 178 { 179 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 180 MT_MEMORY | MT_RW | MT_SECURE); 181 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 182 MT_MEMORY | MT_RO | MT_SECURE); 183 184 /* Map TEE memory */ 185 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 186 187 mmap_add(imx_mmap); 188 189 #if USE_COHERENT_MEM 190 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 191 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 192 MT_DEVICE | MT_RW | MT_SECURE); 193 #endif 194 /* setup xlat table */ 195 init_xlat_tables(); 196 /* enable the MMU */ 197 enable_mmu_el3(0); 198 } 199 200 void bl31_platform_setup(void) 201 { 202 generic_delay_timer_init(); 203 204 /* init the GICv3 cpu and distributor interface */ 205 plat_gic_driver_init(); 206 plat_gic_init(); 207 208 /* determine SOC revision for erratas */ 209 imx8mq_soc_info_init(); 210 211 /* gpc init */ 212 imx_gpc_init(); 213 } 214 215 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 216 { 217 if (type == NON_SECURE) 218 return &bl33_image_ep_info; 219 if (type == SECURE) 220 return &bl32_image_ep_info; 221 222 return NULL; 223 } 224 225 unsigned int plat_get_syscnt_freq2(void) 226 { 227 return COUNTER_FREQUENCY; 228 } 229 230 void bl31_plat_runtime_setup(void) 231 { 232 return; 233 } 234 235 #ifdef SPD_trusty 236 void plat_trusty_set_boot_args(aapcs64_params_t *args) 237 { 238 args->arg0 = BL32_SIZE; 239 args->arg1 = BL32_BASE; 240 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 241 } 242 #endif 243