1# 2# Copyright 2019-2022 NXP 3# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6# 7 8PLAT_INCLUDES := -Iplat/imx/common/include \ 9 -Iplat/imx/imx8m/include \ 10 -Iplat/imx/imx8m/imx8mp/include \ 11 -Idrivers/imx/usdhc \ 12 -Iinclude/common/tbbr 13# Translation tables library 14include lib/xlat_tables_v2/xlat_tables.mk 15 16# Include GICv3 driver files 17include drivers/arm/gic/v3/gicv3.mk 18 19IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \ 20 plat/imx/imx8m/ddr/clock.c \ 21 plat/imx/imx8m/ddr/dram_retention.c \ 22 plat/imx/imx8m/ddr/ddr4_dvfs.c \ 23 plat/imx/imx8m/ddr/lpddr4_dvfs.c 24 25IMX_GIC_SOURCES := ${GICV3_SOURCES} \ 26 plat/common/plat_gicv3.c \ 27 plat/common/plat_psci_common.c \ 28 plat/imx/common/plat_imx8_gic.c 29 30BL31_SOURCES += common/desc_image_load.c \ 31 plat/imx/common/imx8_helpers.S \ 32 plat/imx/imx8m/gpc_common.c \ 33 plat/imx/imx8m/imx_hab.c \ 34 plat/imx/imx8m/imx_aipstz.c \ 35 plat/imx/imx8m/imx_rdc.c \ 36 plat/imx/imx8m/imx8m_caam.c \ 37 plat/imx/imx8m/imx8m_ccm.c \ 38 plat/imx/imx8m/imx8m_csu.c \ 39 plat/imx/imx8m/imx8m_psci_common.c \ 40 plat/imx/imx8m/imx8m_snvs.c \ 41 plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c \ 42 plat/imx/imx8m/imx8mp/imx8mp_psci.c \ 43 plat/imx/imx8m/imx8mp/gpc.c \ 44 plat/imx/common/imx8_topology.c \ 45 plat/imx/common/imx_sip_handler.c \ 46 plat/imx/common/imx_sip_svc.c \ 47 plat/imx/common/imx_common.c \ 48 plat/imx/common/imx_uart_console.S \ 49 lib/cpus/aarch64/cortex_a53.S \ 50 drivers/arm/tzc/tzc380.c \ 51 drivers/delay_timer/delay_timer.c \ 52 drivers/delay_timer/generic_delay_timer.c \ 53 ${IMX_GIC_SOURCES} \ 54 ${XLAT_TABLES_LIB_SRCS} 55 56ifeq (${NEED_BL2},yes) 57BL2_SOURCES += common/desc_image_load.c \ 58 plat/imx/common/imx8_helpers.S \ 59 plat/imx/common/imx_uart_console.S \ 60 plat/imx/imx8m/imx8mp/imx8mp_bl2_setup.c \ 61 plat/imx/imx8m/imx8mp/gpc.c \ 62 plat/imx/imx8m/imx_aipstz.c \ 63 plat/imx/imx8m/imx_rdc.c \ 64 plat/imx/imx8m/imx8m_caam.c \ 65 plat/common/plat_psci_common.c \ 66 lib/cpus/aarch64/cortex_a53.S \ 67 drivers/arm/tzc/tzc380.c \ 68 drivers/delay_timer/delay_timer.c \ 69 drivers/delay_timer/generic_delay_timer.c \ 70 ${PLAT_GIC_SOURCES} \ 71 ${PLAT_DRAM_SOURCES} \ 72 ${XLAT_TABLES_LIB_SRCS} \ 73 drivers/mmc/mmc.c \ 74 drivers/io/io_block.c \ 75 drivers/io/io_fip.c \ 76 drivers/io/io_memmap.c \ 77 drivers/io/io_storage.c \ 78 drivers/imx/usdhc/imx_usdhc.c \ 79 plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c \ 80 plat/imx/common/imx_io_storage.c \ 81 plat/imx/imx8m/imx8m_image_load.c \ 82 lib/optee/optee_utils.c 83endif 84 85# Add the build options to pack BLx images and kernel device tree 86# in the FIP if the platform requires. 87ifneq ($(BL2),) 88RESET_TO_BL31 := 0 89$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) 90endif 91ifneq ($(BL32_EXTRA1),) 92$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) 93endif 94ifneq ($(BL32_EXTRA2),) 95$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) 96endif 97ifneq ($(HW_CONFIG),) 98$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config)) 99endif 100 101ifeq (${NEED_BL2},yes) 102$(eval $(call add_define,NEED_BL2)) 103LOAD_IMAGE_V2 := 1 104# Non-TF Boot ROM 105RESET_TO_BL2 := 1 106endif 107 108ifneq (${TRUSTED_BOARD_BOOT},0) 109 110include drivers/auth/mbedtls/mbedtls_crypto.mk 111include drivers/auth/mbedtls/mbedtls_x509.mk 112 113AUTH_MK := drivers/auth/auth.mk 114$(info Including ${AUTH_MK}) 115include ${AUTH_MK} 116 117AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c \ 118 drivers/auth/tbbr/tbbr_cot_bl2.c 119 120BL2_SOURCES += ${AUTH_SOURCES} \ 121 plat/common/tbbr/plat_tbbr.c \ 122 plat/imx/imx8m/imx8mp/imx8mp_trusted_boot.c \ 123 plat/imx/imx8m/imx8mp/imx8mp_rotpk.S 124 125ROT_KEY = $(BUILD_PLAT)/rot_key.pem 126ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin 127 128$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) 129 130$(BUILD_PLAT)/bl2/imx8mp_rotpk.o: $(ROTPK_HASH) 131 132certificates: $(ROT_KEY) 133 134$(ROT_KEY): | $$(@D)/ 135 $(s)echo " OPENSSL $@" 136 $(q)if [ ! -f $(ROT_KEY) ]; then \ 137 ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ 138 fi 139 140$(ROTPK_HASH): $(ROT_KEY) | $$(@D)/ 141 $(s)echo " OPENSSL $@" 142 $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ 143 ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null 144endif 145 146ENABLE_PIE := 1 147USE_COHERENT_MEM := 1 148RESET_TO_BL31 := 1 149A53_DISABLE_NON_TEMPORAL_HINT := 0 150 151ERRATA_A53_835769 := 1 152ERRATA_A53_843419 := 1 153ERRATA_A53_855873 := 1 154ERRATA_A53_1530924 := 1 155 156IMX_DRAM_RETENTION ?= 1 157$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) 158$(eval $(call add_define,IMX_DRAM_RETENTION)) 159 160ifeq (${IMX_DRAM_RETENTION},1) 161BL31_SOURCES += ${IMX_DRAM_SOURCES} 162endif 163 164ifneq (${PRELOADED_BL33_BASE},) 165$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE})) 166endif 167 168BL32_BASE ?= 0x56000000 169$(eval $(call add_define,BL32_BASE)) 170 171BL32_SIZE ?= 0x2000000 172$(eval $(call add_define,BL32_SIZE)) 173 174IMX_BOOT_UART_BASE ?= 0x30890000 175ifeq (${IMX_BOOT_UART_BASE},auto) 176 override IMX_BOOT_UART_BASE := 0 177endif 178$(eval $(call add_define,IMX_BOOT_UART_BASE)) 179 180EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) 181ifeq (${SDEI_SUPPORT}, 1) 182BL31_SOURCES += plat/imx/common/imx_ehf.c \ 183 plat/imx/common/imx_sdei.c 184endif 185 186ifeq (${SPD},trusty) 187 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 188endif 189