xref: /rk3399_ARM-atf/plat/imx/imx8m/imx8mp/platform.mk (revision 06f3c7058c42a9f1a9f7df75ea2de71a000855e8)
1#
2# Copyright 2019-2022 NXP
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7PLAT_INCLUDES		:=	-Iplat/imx/common/include		\
8				-Iplat/imx/imx8m/include		\
9				-Iplat/imx/imx8m/imx8mp/include		\
10				-Idrivers/imx/usdhc			\
11				-Iinclude/common/tbbr
12# Translation tables library
13include lib/xlat_tables_v2/xlat_tables.mk
14
15# Include GICv3 driver files
16include drivers/arm/gic/v3/gicv3.mk
17
18IMX_DRAM_SOURCES	:=	plat/imx/imx8m/ddr/dram.c		\
19				plat/imx/imx8m/ddr/clock.c		\
20				plat/imx/imx8m/ddr/dram_retention.c	\
21				plat/imx/imx8m/ddr/ddr4_dvfs.c		\
22				plat/imx/imx8m/ddr/lpddr4_dvfs.c
23
24IMX_GIC_SOURCES		:=	${GICV3_SOURCES}			\
25				plat/common/plat_gicv3.c		\
26				plat/common/plat_psci_common.c		\
27				plat/imx/common/plat_imx8_gic.c
28
29BL31_SOURCES		+=	common/desc_image_load.c			\
30				plat/imx/common/imx8_helpers.S			\
31				plat/imx/imx8m/gpc_common.c			\
32				plat/imx/imx8m/imx_hab.c			\
33				plat/imx/imx8m/imx_aipstz.c			\
34				plat/imx/imx8m/imx_rdc.c			\
35				plat/imx/imx8m/imx8m_caam.c			\
36				plat/imx/imx8m/imx8m_ccm.c			\
37				plat/imx/imx8m/imx8m_csu.c			\
38				plat/imx/imx8m/imx8m_psci_common.c		\
39				plat/imx/imx8m/imx8m_snvs.c			\
40				plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c	\
41				plat/imx/imx8m/imx8mp/imx8mp_psci.c		\
42				plat/imx/imx8m/imx8mp/gpc.c			\
43				plat/imx/common/imx8_topology.c			\
44				plat/imx/common/imx_sip_handler.c		\
45				plat/imx/common/imx_sip_svc.c			\
46				plat/imx/common/imx_common.c			\
47				plat/imx/common/imx_uart_console.S		\
48				lib/cpus/aarch64/cortex_a53.S			\
49				drivers/arm/tzc/tzc380.c			\
50				drivers/delay_timer/delay_timer.c		\
51				drivers/delay_timer/generic_delay_timer.c	\
52				${IMX_GIC_SOURCES}				\
53				${XLAT_TABLES_LIB_SRCS}
54
55ifeq (${NEED_BL2},yes)
56BL2_SOURCES		+=	common/desc_image_load.c			\
57				plat/imx/common/imx8_helpers.S			\
58				plat/imx/common/imx_uart_console.S		\
59				plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c	\
60				plat/imx/imx8m/imx8mp/gpc.c			\
61				plat/imx/imx8m/imx_aipstz.c			\
62				plat/imx/imx8m/imx_rdc.c			\
63				plat/imx/imx8m/imx8m_caam.c			\
64				plat/common/plat_psci_common.c			\
65				lib/cpus/aarch64/cortex_a53.S			\
66				drivers/arm/tzc/tzc380.c			\
67				drivers/delay_timer/delay_timer.c		\
68				drivers/delay_timer/generic_delay_timer.c	\
69				${PLAT_GIC_SOURCES}				\
70				${PLAT_DRAM_SOURCES}				\
71				${XLAT_TABLES_LIB_SRCS}				\
72				drivers/mmc/mmc.c				\
73				drivers/io/io_block.c				\
74				drivers/io/io_fip.c				\
75				drivers/io/io_memmap.c				\
76				drivers/io/io_storage.c				\
77				drivers/imx/usdhc/imx_usdhc.c			\
78				plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c	\
79				plat/imx/common/imx_io_storage.c		\
80				plat/imx/imx8m/imx8m_image_load.c		\
81				lib/optee/optee_utils.c
82endif
83
84# Add the build options to pack BLx images and kernel device tree
85# in the FIP if the platform requires.
86ifneq ($(BL2),)
87RESET_TO_BL31		:=	0
88$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
89endif
90ifneq ($(BL32_EXTRA1),)
91$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
92endif
93ifneq ($(BL32_EXTRA2),)
94$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
95endif
96ifneq ($(HW_CONFIG),)
97$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
98endif
99
100ifeq (${NEED_BL2},yes)
101$(eval $(call add_define,NEED_BL2))
102LOAD_IMAGE_V2		:=	1
103# Non-TF Boot ROM
104RESET_TO_BL2		:=	1
105endif
106
107ifneq (${TRUSTED_BOARD_BOOT},0)
108
109include drivers/auth/mbedtls/mbedtls_crypto.mk
110include drivers/auth/mbedtls/mbedtls_x509.mk
111
112AUTH_MK := drivers/auth/auth.mk
113$(info Including ${AUTH_MK})
114include ${AUTH_MK}
115
116AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c     \
117			drivers/auth/tbbr/tbbr_cot_bl2.c
118
119BL2_SOURCES		+=	${AUTH_SOURCES}					\
120				plat/common/tbbr/plat_tbbr.c			\
121				plat/imx/imx8m/imx8mp/imx8mp_trusted_boot.c	\
122				plat/imx/imx8m/imx8mp/imx8mp_rotpk.S
123
124ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
125ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
126
127$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
128
129$(BUILD_PLAT)/bl2/imx8mp_rotpk.o: $(ROTPK_HASH)
130
131certificates: $(ROT_KEY)
132
133$(ROT_KEY): | $$(@D)/
134	$(s)echo "  OPENSSL $@"
135	$(q)if [ ! -f $(ROT_KEY) ]; then \
136		${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
137	fi
138
139$(ROTPK_HASH): $(ROT_KEY) | $$(@D)/
140	$(s)echo "  OPENSSL $@"
141	$(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
142	${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
143endif
144
145ENABLE_PIE		:=	1
146USE_COHERENT_MEM	:=	1
147RESET_TO_BL31		:=	1
148A53_DISABLE_NON_TEMPORAL_HINT := 0
149
150ERRATA_A53_835769	:=	1
151ERRATA_A53_843419	:=	1
152ERRATA_A53_855873	:=	1
153ERRATA_A53_1530924	:=	1
154
155IMX_DRAM_RETENTION	?=	1
156$(eval $(call assert_boolean,IMX_DRAM_RETENTION))
157$(eval $(call add_define,IMX_DRAM_RETENTION))
158
159ifeq (${IMX_DRAM_RETENTION},1)
160BL31_SOURCES		+=	${IMX_DRAM_SOURCES}
161endif
162
163ifneq (${PRELOADED_BL33_BASE},)
164$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
165endif
166
167BL32_BASE		?=	0x56000000
168$(eval $(call add_define,BL32_BASE))
169
170BL32_SIZE		?=	0x2000000
171$(eval $(call add_define,BL32_SIZE))
172
173IMX_BOOT_UART_BASE	?=	0x30890000
174ifeq (${IMX_BOOT_UART_BASE},auto)
175    override IMX_BOOT_UART_BASE	:=	0
176endif
177$(eval $(call add_define,IMX_BOOT_UART_BASE))
178
179EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
180ifeq (${SDEI_SUPPORT}, 1)
181BL31_SOURCES 		+= 	plat/imx/common/imx_ehf.c	\
182				plat/imx/common/imx_sdei.c
183endif
184
185ifeq (${SPD},trusty)
186	BL31_CFLAGS    +=      -DPLAT_XLAT_TABLES_DYNAMIC=1
187endif
188