1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <common/tbbr/tbbr_img_def.h> 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_v2.h> 12 13 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 14 #define PLATFORM_LINKER_ARCH aarch64 15 16 #define PLATFORM_STACK_SIZE 0xB00 17 #define CACHE_WRITEBACK_GRANULE 64 18 19 #define PLAT_PRIMARY_CPU U(0x0) 20 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 21 #define PLATFORM_CLUSTER_COUNT U(1) 22 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 23 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 24 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 25 26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 27 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 28 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 29 30 #define PWR_DOMAIN_AT_MAX_LVL U(1) 31 #define PLAT_MAX_PWR_LVL U(2) 32 #define PLAT_MAX_OFF_STATE U(4) 33 #define PLAT_MAX_RET_STATE U(2) 34 35 #define PLAT_WAIT_RET_STATE U(1) 36 #define PLAT_STOP_OFF_STATE U(3) 37 38 #if defined(NEED_BL2) 39 #define BL2_BASE U(0x970000) 40 #define BL2_LIMIT U(0x990000) 41 #define BL31_BASE U(0x950000) 42 #define BL31_LIMIT U(0x970000) 43 #define IMX_FIP_BASE U(0x40310000) 44 #define IMX_FIP_SIZE U(0x000300000) 45 #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) 46 47 /* Define FIP image location on eMMC */ 48 #define IMX_FIP_MMC_BASE U(0x100000) 49 50 #define PLAT_IMX8MP_BOOT_MMC_BASE U(0x30B50000) /* SD */ 51 #else 52 #define BL31_BASE U(0x970000) 53 #define BL31_LIMIT U(0x990000) 54 #endif 55 56 #define PLAT_PRI_BITS U(3) 57 #define PLAT_SDEI_CRITICAL_PRI 0x10 58 #define PLAT_SDEI_NORMAL_PRI 0x20 59 #define PLAT_SDEI_SGI_PRIVATE U(9) 60 61 /* non-secure uboot base */ 62 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 63 #define PLAT_NS_IMAGE_SIZE U(0x00200000) 64 65 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 66 67 /* GICv3 base address */ 68 #define PLAT_GICD_BASE U(0x38800000) 69 #define PLAT_GICR_BASE U(0x38880000) 70 71 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 72 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 73 74 #define MAX_XLAT_TABLES 8 75 #define MAX_MMAP_REGIONS 16 76 77 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ 78 79 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 80 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 81 #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 82 #define IMX_CONSOLE_BAUDRATE 115200 83 84 #define IMX_AIPSTZ1 U(0x301f0000) 85 #define IMX_AIPSTZ2 U(0x305f0000) 86 #define IMX_AIPSTZ3 U(0x309f0000) 87 #define IMX_AIPSTZ4 U(0x32df0000) 88 #define IMX_AIPSTZ5 U(0x30df0000) 89 90 #define IMX_AIPS_BASE U(0x30000000) 91 #define IMX_AIPS_SIZE U(0x3000000) 92 #define IMX_GPV_BASE U(0x32000000) 93 #define IMX_GPV_SIZE U(0x800000) 94 #define IMX_AIPS1_BASE U(0x30200000) 95 #define IMX_AIPS4_BASE U(0x32c00000) 96 #define IMX_ANAMIX_BASE U(0x30360000) 97 #define IMX_CCM_BASE U(0x30380000) 98 #define IMX_SRC_BASE U(0x30390000) 99 #define IMX_GPC_BASE U(0x303a0000) 100 #define IMX_RDC_BASE U(0x303d0000) 101 #define IMX_CSU_BASE U(0x303e0000) 102 #define IMX_WDOG_BASE U(0x30280000) 103 #define IMX_SNVS_BASE U(0x30370000) 104 #define IMX_NOC_BASE U(0x32700000) 105 #define IMX_NOC_SIZE U(0x100000) 106 #define IMX_TZASC_BASE U(0x32F80000) 107 #define IMX_IOMUX_GPR_BASE U(0x30340000) 108 #define IMX_CAAM_BASE U(0x30900000) 109 #define IMX_DDRC_BASE U(0x3d400000) 110 #define IMX_DDRPHY_BASE U(0x3c000000) 111 #define IMX_DDR_IPS_BASE U(0x3d000000) 112 #define IMX_DDR_IPS_SIZE U(0x1800000) 113 #define IMX_ROM_BASE U(0x0) 114 115 #define IMX_GIC_BASE PLAT_GICD_BASE 116 #define IMX_GIC_SIZE U(0x200000) 117 118 #define IMX_HSIOMIX_CTL_BASE U(0x32f10000) 119 #define IMX_HDMI_CTL_BASE U(0x32fc0000) 120 #define RTX_RESET_CTL0 U(0x20) 121 #define RTX_CLK_CTL0 U(0x40) 122 #define RTX_CLK_CTL1 U(0x50) 123 #define TX_CONTROL0 U(0x200) 124 #define TX_CONTROL1 U(0x220) 125 126 #define IMX_MEDIAMIX_CTL_BASE U(0x32ec0000) 127 #define RSTn_CSR U(0x0) 128 #define CLK_EN_CSR U(0x4) 129 #define RST_DIV U(0x8) 130 #define LCDIF_ARCACHE_CTRL U(0x4c) 131 #define ISI_CACHE_CTRL U(0x50) 132 133 #define WDOG_WSR U(0x2) 134 #define WDOG_WCR_WDZST BIT(0) 135 #define WDOG_WCR_WDBG BIT(1) 136 #define WDOG_WCR_WDE BIT(2) 137 #define WDOG_WCR_WDT BIT(3) 138 #define WDOG_WCR_SRS BIT(4) 139 #define WDOG_WCR_WDA BIT(5) 140 #define WDOG_WCR_SRE BIT(6) 141 #define WDOG_WCR_WDW BIT(7) 142 143 #define SRC_A53RCR0 U(0x4) 144 #define SRC_A53RCR1 U(0x8) 145 #define SRC_OTG1PHY_SCR U(0x20) 146 #define SRC_OTG2PHY_SCR U(0x24) 147 #define SRC_GPR1_OFFSET U(0x74) 148 149 #define SNVS_LPCR U(0x38) 150 #define SNVS_LPCR_SRTC_ENV BIT(0) 151 #define SNVS_LPCR_DP_EN BIT(5) 152 #define SNVS_LPCR_TOP BIT(6) 153 154 #define IOMUXC_GPR10 U(0x28) 155 #define GPR_TZASC_EN BIT(0) 156 #define GPR_TZASC_EN_LOCK BIT(16) 157 158 #define ANAMIX_MISC_CTL U(0x124) 159 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) 160 161 #define MAX_CSU_NUM U(64) 162 163 #define OCRAM_S_BASE U(0x00180000) 164 #define OCRAM_S_SIZE U(0x8000) 165 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 166 #define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE 167 168 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 169 170 #define IMX_WDOG_B_RESET 171 172 #define MAX_IO_HANDLES 3U 173 #define MAX_IO_DEVICES 2U 174 #define MAX_IO_BLOCK_DEVICES 1U 175 176 #define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW) 177 #define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ 178 #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */ 179 #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ 180 #define NOC_MAP MAP_REGION_FLAT(IMX_NOC_BASE, IMX_NOC_SIZE, MT_DEVICE | MT_RW) /* NOC QoS */ 181 182 #endif /* platform_def.h */ 183