1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <platform_def.h> 28 #include <plat_imx8.h> 29 30 static const mmap_region_t imx_mmap[] = { 31 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 32 NOC_MAP, {0}, 33 }; 34 35 static const struct aipstz_cfg aipstz[] = { 36 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 37 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {0}, 41 }; 42 43 static const struct imx_rdc_cfg rdc[] = { 44 /* Master domain assignment */ 45 RDC_MDAn(RDC_MDA_M7, DID1), 46 47 /* peripherals domain permission */ 48 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 49 50 /* memory region */ 51 52 /* Sentinel */ 53 {0}, 54 }; 55 56 static entry_point_info_t bl32_image_ep_info; 57 static entry_point_info_t bl33_image_ep_info; 58 59 /* get SPSR for BL33 entry */ 60 static uint32_t get_spsr_for_bl33_entry(void) 61 { 62 unsigned long el_status; 63 unsigned long mode; 64 uint32_t spsr; 65 66 /* figure out what mode we enter the non-secure world */ 67 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 68 el_status &= ID_AA64PFR0_ELX_MASK; 69 70 mode = (el_status) ? MODE_EL2 : MODE_EL1; 71 72 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 73 return spsr; 74 } 75 76 static void bl31_tzc380_setup(void) 77 { 78 unsigned int val; 79 80 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 81 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 82 return; 83 84 tzc380_init(IMX_TZASC_BASE); 85 86 /* 87 * Need to substact offset 0x40000000 from CPU address when 88 * programming tzasc region for i.mx8mp. 89 */ 90 91 /* Enable 1G-5G S/NS RW */ 92 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 93 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 94 } 95 96 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 97 u_register_t arg2, u_register_t arg3) 98 { 99 static console_t console; 100 unsigned int i; 101 102 /* Enable CSU NS access permission */ 103 for (i = 0; i < 64; i++) { 104 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 105 } 106 107 imx_aipstz_init(aipstz); 108 109 imx_rdc_init(rdc); 110 111 imx8m_caam_init(); 112 113 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 114 IMX_CONSOLE_BAUDRATE, &console); 115 /* This console is only used for boot stage */ 116 console_set_scope(&console, CONSOLE_FLAG_BOOT); 117 118 /* 119 * tell BL3-1 where the non-secure software image is located 120 * and the entry state information. 121 */ 122 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 123 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 124 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 125 126 #ifdef SPD_opteed 127 /* Populate entry point information for BL32 */ 128 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 129 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 130 bl32_image_ep_info.pc = BL32_BASE; 131 bl32_image_ep_info.spsr = 0; 132 133 /* Pass TEE base and size to bl33 */ 134 bl33_image_ep_info.args.arg1 = BL32_BASE; 135 bl33_image_ep_info.args.arg2 = BL32_SIZE; 136 #endif 137 138 bl31_tzc380_setup(); 139 } 140 141 void bl31_plat_arch_setup(void) 142 { 143 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 144 MT_MEMORY | MT_RW | MT_SECURE); 145 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 146 MT_MEMORY | MT_RO | MT_SECURE); 147 #if USE_COHERENT_MEM 148 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 149 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 150 MT_DEVICE | MT_RW | MT_SECURE); 151 #endif 152 mmap_add(imx_mmap); 153 154 init_xlat_tables(); 155 156 enable_mmu_el3(0); 157 } 158 159 void bl31_platform_setup(void) 160 { 161 generic_delay_timer_init(); 162 163 /* select the CKIL source to 32K OSC */ 164 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 165 166 plat_gic_driver_init(); 167 plat_gic_init(); 168 169 imx_gpc_init(); 170 } 171 172 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 173 { 174 if (type == NON_SECURE) { 175 return &bl33_image_ep_info; 176 } 177 178 if (type == SECURE) { 179 return &bl32_image_ep_info; 180 } 181 182 return NULL; 183 } 184 185 unsigned int plat_get_syscnt_freq2(void) 186 { 187 return COUNTER_FREQUENCY; 188 } 189