1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_imx8.h> 33 34 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 35 36 static const mmap_region_t imx_mmap[] = { 37 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 38 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 39 ROM_MAP, DRAM_MAP, 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static const struct imx_rdc_cfg rdc[] = { 52 /* Master domain assignment */ 53 RDC_MDAn(RDC_MDA_M7, DID1), 54 55 /* peripherals domain permission */ 56 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 57 58 /* memory region */ 59 60 /* Sentinel */ 61 {0}, 62 }; 63 64 static const struct imx_csu_cfg csu_cfg[] = { 65 /* peripherals csl setting */ 66 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 67 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 68 69 /* master HP0~1 */ 70 71 /* SA setting */ 72 CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED), 73 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 74 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 75 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 76 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 77 CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED), 78 CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED), 79 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 80 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 81 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 82 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 83 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 84 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 85 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 86 CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED), 87 CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED), 102 103 /* HP control setting */ 104 105 /* Sentinel */ 106 {0} 107 }; 108 109 static entry_point_info_t bl32_image_ep_info; 110 static entry_point_info_t bl33_image_ep_info; 111 112 /* get SPSR for BL33 entry */ 113 static uint32_t get_spsr_for_bl33_entry(void) 114 { 115 unsigned long el_status; 116 unsigned long mode; 117 uint32_t spsr; 118 119 /* figure out what mode we enter the non-secure world */ 120 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 121 el_status &= ID_AA64PFR0_ELX_MASK; 122 123 mode = (el_status) ? MODE_EL2 : MODE_EL1; 124 125 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 126 return spsr; 127 } 128 129 static void bl31_tzc380_setup(void) 130 { 131 unsigned int val; 132 133 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 134 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 135 return; 136 137 tzc380_init(IMX_TZASC_BASE); 138 139 /* 140 * Need to substact offset 0x40000000 from CPU address when 141 * programming tzasc region for i.mx8mp. 142 */ 143 144 /* Enable 1G-5G S/NS RW */ 145 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 146 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 147 } 148 149 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 150 u_register_t arg2, u_register_t arg3) 151 { 152 unsigned int console_base = IMX_BOOT_UART_BASE; 153 static console_t console; 154 unsigned int val; 155 unsigned int i; 156 157 /* Enable CSU NS access permission */ 158 for (i = 0; i < 64; i++) { 159 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 160 } 161 162 imx_aipstz_init(aipstz); 163 164 imx_rdc_init(rdc); 165 166 imx_csu_init(csu_cfg); 167 168 /* config the ocram memory range for secure access */ 169 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 170 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 171 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 172 173 if (console_base == 0U) { 174 console_base = imx8m_uart_get_base(); 175 } 176 177 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 178 IMX_CONSOLE_BAUDRATE, &console); 179 /* This console is only used for boot stage */ 180 console_set_scope(&console, CONSOLE_FLAG_BOOT); 181 182 imx8m_caam_init(); 183 184 /* 185 * tell BL3-1 where the non-secure software image is located 186 * and the entry state information. 187 */ 188 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 189 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 190 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 191 192 #if defined(SPD_opteed) || defined(SPD_trusty) 193 /* Populate entry point information for BL32 */ 194 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 195 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 196 bl32_image_ep_info.pc = BL32_BASE; 197 bl32_image_ep_info.spsr = 0; 198 199 /* Pass TEE base and size to bl33 */ 200 bl33_image_ep_info.args.arg1 = BL32_BASE; 201 bl33_image_ep_info.args.arg2 = BL32_SIZE; 202 203 #ifdef SPD_trusty 204 bl32_image_ep_info.args.arg0 = BL32_SIZE; 205 bl32_image_ep_info.args.arg1 = BL32_BASE; 206 #else 207 /* Make sure memory is clean */ 208 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 209 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 210 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 211 #endif 212 #endif 213 214 #if !defined(SPD_opteed) && !defined(SPD_trusty) 215 enable_snvs_privileged_access(); 216 #endif 217 218 bl31_tzc380_setup(); 219 } 220 221 #define MAP_BL31_TOTAL \ 222 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 223 #define MAP_BL31_RO \ 224 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 225 #define MAP_COHERENT_MEM \ 226 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 227 MT_DEVICE | MT_RW | MT_SECURE) 228 #define MAP_BL32_TOTAL \ 229 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 230 231 void bl31_plat_arch_setup(void) 232 { 233 const mmap_region_t bl_regions[] = { 234 MAP_BL31_TOTAL, 235 MAP_BL31_RO, 236 #if USE_COHERENT_MEM 237 MAP_COHERENT_MEM, 238 #endif 239 #if defined(SPD_opteed) || defined(SPD_trusty) 240 /* Map TEE memory */ 241 MAP_BL32_TOTAL, 242 #endif 243 {0} 244 }; 245 246 setup_page_tables(bl_regions, imx_mmap); 247 enable_mmu_el3(0); 248 } 249 250 void bl31_platform_setup(void) 251 { 252 generic_delay_timer_init(); 253 254 /* select the CKIL source to 32K OSC */ 255 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 256 257 /* Init the dram info */ 258 dram_info_init(SAVED_DRAM_TIMING_BASE); 259 260 plat_gic_driver_init(); 261 plat_gic_init(); 262 263 imx_gpc_init(); 264 } 265 266 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 267 { 268 if (type == NON_SECURE) { 269 return &bl33_image_ep_info; 270 } 271 272 if (type == SECURE) { 273 return &bl32_image_ep_info; 274 } 275 276 return NULL; 277 } 278 279 unsigned int plat_get_syscnt_freq2(void) 280 { 281 return COUNTER_FREQUENCY; 282 } 283 284 #ifdef SPD_trusty 285 void plat_trusty_set_boot_args(aapcs64_params_t *args) 286 { 287 args->arg0 = BL32_SIZE; 288 args->arg1 = BL32_BASE; 289 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 290 } 291 #endif 292