1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_imx8.h> 33 34 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 35 36 static const mmap_region_t imx_mmap[] = { 37 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 38 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 39 ROM_MAP, DRAM_MAP, 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static const struct imx_rdc_cfg rdc[] = { 52 /* Master domain assignment */ 53 RDC_MDAn(RDC_MDA_M7, DID1), 54 55 /* peripherals domain permission */ 56 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 57 58 /* memory region */ 59 60 /* Sentinel */ 61 {0}, 62 }; 63 64 static const struct imx_csu_cfg csu_cfg[] = { 65 /* peripherals csl setting */ 66 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 67 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 68 69 /* master HP0~1 */ 70 71 /* SA setting */ 72 73 /* HP control setting */ 74 75 /* Sentinel */ 76 {0} 77 }; 78 79 static entry_point_info_t bl32_image_ep_info; 80 static entry_point_info_t bl33_image_ep_info; 81 82 /* get SPSR for BL33 entry */ 83 static uint32_t get_spsr_for_bl33_entry(void) 84 { 85 unsigned long el_status; 86 unsigned long mode; 87 uint32_t spsr; 88 89 /* figure out what mode we enter the non-secure world */ 90 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 91 el_status &= ID_AA64PFR0_ELX_MASK; 92 93 mode = (el_status) ? MODE_EL2 : MODE_EL1; 94 95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 96 return spsr; 97 } 98 99 static void bl31_tzc380_setup(void) 100 { 101 unsigned int val; 102 103 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 104 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 105 return; 106 107 tzc380_init(IMX_TZASC_BASE); 108 109 /* 110 * Need to substact offset 0x40000000 from CPU address when 111 * programming tzasc region for i.mx8mp. 112 */ 113 114 /* Enable 1G-5G S/NS RW */ 115 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 116 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 117 } 118 119 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 120 u_register_t arg2, u_register_t arg3) 121 { 122 unsigned int console_base = IMX_BOOT_UART_BASE; 123 static console_t console; 124 unsigned int val; 125 unsigned int i; 126 127 /* Enable CSU NS access permission */ 128 for (i = 0; i < 64; i++) { 129 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 130 } 131 132 imx_aipstz_init(aipstz); 133 134 imx_rdc_init(rdc); 135 136 imx_csu_init(csu_cfg); 137 138 /* config the ocram memory range for secure access */ 139 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 140 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 141 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 142 143 if (console_base == 0U) { 144 console_base = imx8m_uart_get_base(); 145 } 146 147 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 148 IMX_CONSOLE_BAUDRATE, &console); 149 /* This console is only used for boot stage */ 150 console_set_scope(&console, CONSOLE_FLAG_BOOT); 151 152 imx8m_caam_init(); 153 154 /* 155 * tell BL3-1 where the non-secure software image is located 156 * and the entry state information. 157 */ 158 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 159 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 160 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 161 162 #if defined(SPD_opteed) || defined(SPD_trusty) 163 /* Populate entry point information for BL32 */ 164 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 165 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 166 bl32_image_ep_info.pc = BL32_BASE; 167 bl32_image_ep_info.spsr = 0; 168 169 /* Pass TEE base and size to bl33 */ 170 bl33_image_ep_info.args.arg1 = BL32_BASE; 171 bl33_image_ep_info.args.arg2 = BL32_SIZE; 172 173 #ifdef SPD_trusty 174 bl32_image_ep_info.args.arg0 = BL32_SIZE; 175 bl32_image_ep_info.args.arg1 = BL32_BASE; 176 #else 177 /* Make sure memory is clean */ 178 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 179 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 180 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 181 #endif 182 #endif 183 184 #if !defined(SPD_opteed) && !defined(SPD_trusty) 185 enable_snvs_privileged_access(); 186 #endif 187 188 bl31_tzc380_setup(); 189 } 190 191 #define MAP_BL31_TOTAL \ 192 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 193 #define MAP_BL31_RO \ 194 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 195 #define MAP_COHERENT_MEM \ 196 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 197 MT_DEVICE | MT_RW | MT_SECURE) 198 #define MAP_BL32_TOTAL \ 199 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 200 201 void bl31_plat_arch_setup(void) 202 { 203 const mmap_region_t bl_regions[] = { 204 MAP_BL31_TOTAL, 205 MAP_BL31_RO, 206 #if USE_COHERENT_MEM 207 MAP_COHERENT_MEM, 208 #endif 209 #if defined(SPD_opteed) || defined(SPD_trusty) 210 /* Map TEE memory */ 211 MAP_BL32_TOTAL, 212 #endif 213 {0} 214 }; 215 216 setup_page_tables(bl_regions, imx_mmap); 217 enable_mmu_el3(0); 218 } 219 220 void bl31_platform_setup(void) 221 { 222 generic_delay_timer_init(); 223 224 /* select the CKIL source to 32K OSC */ 225 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 226 227 /* Init the dram info */ 228 dram_info_init(SAVED_DRAM_TIMING_BASE); 229 230 plat_gic_driver_init(); 231 plat_gic_init(); 232 233 imx_gpc_init(); 234 } 235 236 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 237 { 238 if (type == NON_SECURE) { 239 return &bl33_image_ep_info; 240 } 241 242 if (type == SECURE) { 243 return &bl32_image_ep_info; 244 } 245 246 return NULL; 247 } 248 249 unsigned int plat_get_syscnt_freq2(void) 250 { 251 return COUNTER_FREQUENCY; 252 } 253 254 #ifdef SPD_trusty 255 void plat_trusty_set_boot_args(aapcs64_params_t *args) 256 { 257 args->arg0 = BL32_SIZE; 258 args->arg1 = BL32_BASE; 259 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 260 } 261 #endif 262