1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <imx8m_csu.h> 28 #include <platform_def.h> 29 #include <plat_imx8.h> 30 31 static const mmap_region_t imx_mmap[] = { 32 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 33 NOC_MAP, {0}, 34 }; 35 36 static const struct aipstz_cfg aipstz[] = { 37 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {0}, 42 }; 43 44 static const struct imx_rdc_cfg rdc[] = { 45 /* Master domain assignment */ 46 RDC_MDAn(RDC_MDA_M7, DID1), 47 48 /* peripherals domain permission */ 49 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 50 51 /* memory region */ 52 53 /* Sentinel */ 54 {0}, 55 }; 56 57 static const struct imx_csu_cfg csu_cfg[] = { 58 /* peripherals csl setting */ 59 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 60 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 61 62 /* master HP0~1 */ 63 64 /* SA setting */ 65 66 /* HP control setting */ 67 68 /* Sentinel */ 69 {0} 70 }; 71 72 static entry_point_info_t bl32_image_ep_info; 73 static entry_point_info_t bl33_image_ep_info; 74 75 /* get SPSR for BL33 entry */ 76 static uint32_t get_spsr_for_bl33_entry(void) 77 { 78 unsigned long el_status; 79 unsigned long mode; 80 uint32_t spsr; 81 82 /* figure out what mode we enter the non-secure world */ 83 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 84 el_status &= ID_AA64PFR0_ELX_MASK; 85 86 mode = (el_status) ? MODE_EL2 : MODE_EL1; 87 88 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 89 return spsr; 90 } 91 92 static void bl31_tzc380_setup(void) 93 { 94 unsigned int val; 95 96 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 97 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 98 return; 99 100 tzc380_init(IMX_TZASC_BASE); 101 102 /* 103 * Need to substact offset 0x40000000 from CPU address when 104 * programming tzasc region for i.mx8mp. 105 */ 106 107 /* Enable 1G-5G S/NS RW */ 108 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 109 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 110 } 111 112 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 113 u_register_t arg2, u_register_t arg3) 114 { 115 static console_t console; 116 unsigned int val; 117 unsigned int i; 118 119 /* Enable CSU NS access permission */ 120 for (i = 0; i < 64; i++) { 121 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 122 } 123 124 imx_aipstz_init(aipstz); 125 126 imx_rdc_init(rdc); 127 128 imx_csu_init(csu_cfg); 129 130 /* config the ocram memory range for secure access */ 131 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 132 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 133 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 134 135 imx8m_caam_init(); 136 137 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 138 IMX_CONSOLE_BAUDRATE, &console); 139 /* This console is only used for boot stage */ 140 console_set_scope(&console, CONSOLE_FLAG_BOOT); 141 142 /* 143 * tell BL3-1 where the non-secure software image is located 144 * and the entry state information. 145 */ 146 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 147 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 148 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 149 150 #ifdef SPD_opteed 151 /* Populate entry point information for BL32 */ 152 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 153 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 154 bl32_image_ep_info.pc = BL32_BASE; 155 bl32_image_ep_info.spsr = 0; 156 157 /* Pass TEE base and size to bl33 */ 158 bl33_image_ep_info.args.arg1 = BL32_BASE; 159 bl33_image_ep_info.args.arg2 = BL32_SIZE; 160 #endif 161 162 bl31_tzc380_setup(); 163 } 164 165 void bl31_plat_arch_setup(void) 166 { 167 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 168 MT_MEMORY | MT_RW | MT_SECURE); 169 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 170 MT_MEMORY | MT_RO | MT_SECURE); 171 #if USE_COHERENT_MEM 172 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 173 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 174 MT_DEVICE | MT_RW | MT_SECURE); 175 #endif 176 mmap_add(imx_mmap); 177 178 init_xlat_tables(); 179 180 enable_mmu_el3(0); 181 } 182 183 void bl31_platform_setup(void) 184 { 185 generic_delay_timer_init(); 186 187 /* select the CKIL source to 32K OSC */ 188 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 189 190 plat_gic_driver_init(); 191 plat_gic_init(); 192 193 imx_gpc_init(); 194 } 195 196 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 197 { 198 if (type == NON_SECURE) { 199 return &bl33_image_ep_info; 200 } 201 202 if (type == SECURE) { 203 return &bl32_image_ep_info; 204 } 205 206 return NULL; 207 } 208 209 unsigned int plat_get_syscnt_freq2(void) 210 { 211 return COUNTER_FREQUENCY; 212 } 213