1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_common.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 static const mmap_region_t imx_mmap[] = { 38 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 39 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 40 ROM_MAP, DRAM_MAP, 41 {0}, 42 }; 43 44 static const struct aipstz_cfg aipstz[] = { 45 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 49 {0}, 50 }; 51 52 static struct imx_rdc_cfg rdc[] = { 53 /* Master domain assignment */ 54 RDC_MDAn(RDC_MDA_M7, DID1), 55 56 /* peripherals domain permission */ 57 RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W), 58 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 59 RDC_PDAPn(RDC_PDAP_UART3, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W), 60 RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W), 61 RDC_PDAPn(RDC_PDAP_WDOG1, D0R | D0W), 62 63 /* memory region */ 64 65 /* Sentinel */ 66 {0}, 67 }; 68 69 static const struct imx_csu_cfg csu_cfg[] = { 70 /* peripherals csl setting */ 71 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED), 72 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED), 73 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 74 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 75 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 76 77 /* master HP0~1 */ 78 79 /* SA setting */ 80 CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED), 81 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 82 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 83 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 84 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 85 CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED), 86 CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED), 87 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED), 105 CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED), 106 CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED), 107 CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED), 108 CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED), 109 CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED), 110 111 /* HP control setting */ 112 113 /* Sentinel */ 114 {0} 115 }; 116 117 static entry_point_info_t bl32_image_ep_info; 118 static entry_point_info_t bl33_image_ep_info; 119 120 /* get SPSR for BL33 entry */ 121 static uint32_t get_spsr_for_bl33_entry(void) 122 { 123 unsigned long el_status; 124 unsigned long mode; 125 uint32_t spsr; 126 127 /* figure out what mode we enter the non-secure world */ 128 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 129 el_status &= ID_AA64PFR0_ELX_MASK; 130 131 mode = (el_status) ? MODE_EL2 : MODE_EL1; 132 133 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 134 return spsr; 135 } 136 137 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 138 u_register_t arg2, u_register_t arg3) 139 { 140 unsigned int console_base = IMX_BOOT_UART_BASE; 141 static console_t console; 142 unsigned int val; 143 unsigned int i; 144 int ret; 145 146 /* Enable CSU NS access permission */ 147 for (i = 0; i < 64; i++) { 148 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 149 } 150 151 imx_aipstz_init(aipstz); 152 153 if (console_base == 0U) { 154 console_base = imx8m_uart_get_base(); 155 } 156 157 imx_rdc_init(rdc, console_base); 158 159 imx_csu_init(csu_cfg); 160 161 /* config the ocram memory range for secure access */ 162 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 163 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 164 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 165 166 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 167 IMX_CONSOLE_BAUDRATE, &console); 168 /* This console is only used for boot stage */ 169 console_set_scope(&console, CONSOLE_FLAG_BOOT); 170 171 imx8m_caam_init(); 172 173 /* 174 * tell BL3-1 where the non-secure software image is located 175 * and the entry state information. 176 */ 177 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 178 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 179 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 180 181 #if defined(SPD_opteed) || defined(SPD_trusty) 182 /* Populate entry point information for BL32 */ 183 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 184 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 185 bl32_image_ep_info.pc = BL32_BASE; 186 bl32_image_ep_info.spsr = 0; 187 188 /* Pass TEE base and size to bl33 */ 189 bl33_image_ep_info.args.arg1 = BL32_BASE; 190 bl33_image_ep_info.args.arg2 = BL32_SIZE; 191 192 #ifdef SPD_trusty 193 bl32_image_ep_info.args.arg0 = BL32_SIZE; 194 bl32_image_ep_info.args.arg1 = BL32_BASE; 195 #else 196 /* Make sure memory is clean */ 197 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 198 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 199 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 200 #endif 201 #endif 202 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 203 &bl32_image_ep_info, &bl33_image_ep_info); 204 if (ret != 0) { 205 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 206 &bl32_image_ep_info, 207 &bl33_image_ep_info); 208 } 209 210 #if !defined(SPD_opteed) && !defined(SPD_trusty) 211 enable_snvs_privileged_access(); 212 #endif 213 } 214 215 #define MAP_BL31_TOTAL \ 216 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 217 #define MAP_BL31_RO \ 218 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 219 #define MAP_COHERENT_MEM \ 220 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 221 MT_DEVICE | MT_RW | MT_SECURE) 222 #define MAP_BL32_TOTAL \ 223 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 224 225 void bl31_plat_arch_setup(void) 226 { 227 const mmap_region_t bl_regions[] = { 228 MAP_BL31_TOTAL, 229 MAP_BL31_RO, 230 #if USE_COHERENT_MEM 231 MAP_COHERENT_MEM, 232 #endif 233 #if defined(SPD_opteed) || defined(SPD_trusty) 234 /* Map TEE memory */ 235 MAP_BL32_TOTAL, 236 #endif 237 {0} 238 }; 239 240 setup_page_tables(bl_regions, imx_mmap); 241 enable_mmu_el3(0); 242 } 243 244 void bl31_platform_setup(void) 245 { 246 generic_delay_timer_init(); 247 248 /* select the CKIL source to 32K OSC */ 249 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 250 251 /* Init the dram info */ 252 dram_info_init(SAVED_DRAM_TIMING_BASE); 253 254 plat_gic_driver_init(); 255 plat_gic_init(); 256 257 imx_gpc_init(); 258 } 259 260 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 261 { 262 if (type == NON_SECURE) { 263 return &bl33_image_ep_info; 264 } 265 266 if (type == SECURE) { 267 return &bl32_image_ep_info; 268 } 269 270 return NULL; 271 } 272 273 unsigned int plat_get_syscnt_freq2(void) 274 { 275 return COUNTER_FREQUENCY; 276 } 277 278 #ifdef SPD_trusty 279 void plat_trusty_set_boot_args(aapcs64_params_t *args) 280 { 281 args->arg0 = BL32_SIZE; 282 args->arg1 = BL32_BASE; 283 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 284 } 285 #endif 286