1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_common.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 static const mmap_region_t imx_mmap[] = { 38 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 39 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 40 ROM_MAP, DRAM_MAP, 41 {0}, 42 }; 43 44 static const struct aipstz_cfg aipstz[] = { 45 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 49 {0}, 50 }; 51 52 static struct imx_rdc_cfg rdc[] = { 53 /* Master domain assignment */ 54 RDC_MDAn(RDC_MDA_M7, DID1), 55 56 /* peripherals domain permission */ 57 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 58 59 /* memory region */ 60 61 /* Sentinel */ 62 {0}, 63 }; 64 65 static const struct imx_csu_cfg csu_cfg[] = { 66 /* peripherals csl setting */ 67 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED), 68 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED), 69 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 70 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 71 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 72 73 /* master HP0~1 */ 74 75 /* SA setting */ 76 CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED), 77 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 78 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 79 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 80 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 81 CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED), 82 CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED), 83 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 84 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 85 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 86 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 87 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED), 105 CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED), 106 107 /* HP control setting */ 108 109 /* Sentinel */ 110 {0} 111 }; 112 113 static entry_point_info_t bl32_image_ep_info; 114 static entry_point_info_t bl33_image_ep_info; 115 116 /* get SPSR for BL33 entry */ 117 static uint32_t get_spsr_for_bl33_entry(void) 118 { 119 unsigned long el_status; 120 unsigned long mode; 121 uint32_t spsr; 122 123 /* figure out what mode we enter the non-secure world */ 124 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 125 el_status &= ID_AA64PFR0_ELX_MASK; 126 127 mode = (el_status) ? MODE_EL2 : MODE_EL1; 128 129 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 130 return spsr; 131 } 132 133 static void bl31_tzc380_setup(void) 134 { 135 unsigned int val; 136 137 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 138 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 139 return; 140 141 tzc380_init(IMX_TZASC_BASE); 142 143 /* 144 * Need to substact offset 0x40000000 from CPU address when 145 * programming tzasc region for i.mx8mp. 146 */ 147 148 /* Enable 1G-5G S/NS RW */ 149 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 150 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 151 } 152 153 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 154 u_register_t arg2, u_register_t arg3) 155 { 156 unsigned int console_base = IMX_BOOT_UART_BASE; 157 static console_t console; 158 unsigned int val; 159 unsigned int i; 160 int ret; 161 162 /* Enable CSU NS access permission */ 163 for (i = 0; i < 64; i++) { 164 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 165 } 166 167 imx_aipstz_init(aipstz); 168 169 if (console_base == 0U) { 170 console_base = imx8m_uart_get_base(); 171 } 172 173 imx_rdc_init(rdc, console_base); 174 175 imx_csu_init(csu_cfg); 176 177 /* config the ocram memory range for secure access */ 178 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 179 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 180 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 181 182 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 183 IMX_CONSOLE_BAUDRATE, &console); 184 /* This console is only used for boot stage */ 185 console_set_scope(&console, CONSOLE_FLAG_BOOT); 186 187 imx8m_caam_init(); 188 189 /* 190 * tell BL3-1 where the non-secure software image is located 191 * and the entry state information. 192 */ 193 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 194 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 195 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 196 197 #if defined(SPD_opteed) || defined(SPD_trusty) 198 /* Populate entry point information for BL32 */ 199 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 200 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 201 bl32_image_ep_info.pc = BL32_BASE; 202 bl32_image_ep_info.spsr = 0; 203 204 /* Pass TEE base and size to bl33 */ 205 bl33_image_ep_info.args.arg1 = BL32_BASE; 206 bl33_image_ep_info.args.arg2 = BL32_SIZE; 207 208 #ifdef SPD_trusty 209 bl32_image_ep_info.args.arg0 = BL32_SIZE; 210 bl32_image_ep_info.args.arg1 = BL32_BASE; 211 #else 212 /* Make sure memory is clean */ 213 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 214 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 215 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 216 #endif 217 #endif 218 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 219 &bl32_image_ep_info, &bl33_image_ep_info); 220 if (ret != 0) { 221 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 222 &bl32_image_ep_info, 223 &bl33_image_ep_info); 224 } 225 226 #if !defined(SPD_opteed) && !defined(SPD_trusty) 227 enable_snvs_privileged_access(); 228 #endif 229 230 bl31_tzc380_setup(); 231 } 232 233 #define MAP_BL31_TOTAL \ 234 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 235 #define MAP_BL31_RO \ 236 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 237 #define MAP_COHERENT_MEM \ 238 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 239 MT_DEVICE | MT_RW | MT_SECURE) 240 #define MAP_BL32_TOTAL \ 241 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 242 243 void bl31_plat_arch_setup(void) 244 { 245 const mmap_region_t bl_regions[] = { 246 MAP_BL31_TOTAL, 247 MAP_BL31_RO, 248 #if USE_COHERENT_MEM 249 MAP_COHERENT_MEM, 250 #endif 251 #if defined(SPD_opteed) || defined(SPD_trusty) 252 /* Map TEE memory */ 253 MAP_BL32_TOTAL, 254 #endif 255 {0} 256 }; 257 258 setup_page_tables(bl_regions, imx_mmap); 259 enable_mmu_el3(0); 260 } 261 262 void bl31_platform_setup(void) 263 { 264 generic_delay_timer_init(); 265 266 /* select the CKIL source to 32K OSC */ 267 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 268 269 /* Init the dram info */ 270 dram_info_init(SAVED_DRAM_TIMING_BASE); 271 272 plat_gic_driver_init(); 273 plat_gic_init(); 274 275 imx_gpc_init(); 276 } 277 278 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 279 { 280 if (type == NON_SECURE) { 281 return &bl33_image_ep_info; 282 } 283 284 if (type == SECURE) { 285 return &bl32_image_ep_info; 286 } 287 288 return NULL; 289 } 290 291 unsigned int plat_get_syscnt_freq2(void) 292 { 293 return COUNTER_FREQUENCY; 294 } 295 296 #ifdef SPD_trusty 297 void plat_trusty_set_boot_args(aapcs64_params_t *args) 298 { 299 args->arg0 = BL32_SIZE; 300 args->arg1 = BL32_BASE; 301 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 302 } 303 #endif 304