1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/mmio.h> 22 #include <lib/optee_utils.h> 23 #include <lib/xlat_tables/xlat_tables_v2.h> 24 25 #include <imx8m_caam.h> 26 #include "imx8mp_private.h" 27 #include <imx_aipstz.h> 28 #include <imx_rdc.h> 29 #include <imx_uart.h> 30 #include <plat/common/platform.h> 31 #include <plat_imx8.h> 32 #include <platform_def.h> 33 34 35 static const struct aipstz_cfg aipstz[] = { 36 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 37 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {0}, 41 }; 42 43 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 44 u_register_t arg2, u_register_t arg3) 45 { 46 static console_t console; 47 unsigned int i; 48 49 /* Enable CSU NS access permission */ 50 for (i = 0U; i < 64; i++) { 51 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 52 } 53 54 imx_aipstz_init(aipstz); 55 56 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 57 IMX_CONSOLE_BAUDRATE, &console); 58 59 generic_delay_timer_init(); 60 61 /* select the CKIL source to 32K OSC */ 62 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 63 64 /* Open handles to a FIP image */ 65 plat_imx_io_setup(); 66 } 67 68 void bl2_el3_plat_arch_setup(void) 69 { 70 } 71 72 void bl2_platform_setup(void) 73 { 74 } 75 76 int bl2_plat_handle_post_image_load(unsigned int image_id) 77 { 78 int err = 0; 79 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 80 bl_mem_params_node_t *pager_mem_params = NULL; 81 bl_mem_params_node_t *paged_mem_params = NULL; 82 83 assert(bl_mem_params); 84 85 switch (image_id) { 86 case BL32_IMAGE_ID: 87 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 88 assert(pager_mem_params); 89 90 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 91 assert(paged_mem_params); 92 93 err = parse_optee_header(&bl_mem_params->ep_info, 94 &pager_mem_params->image_info, 95 &paged_mem_params->image_info); 96 if (err != 0) { 97 WARN("OPTEE header parse error.\n"); 98 } 99 100 break; 101 default: 102 /* Do nothing in default case */ 103 break; 104 } 105 106 return err; 107 } 108 109 unsigned int plat_get_syscnt_freq2(void) 110 { 111 return COUNTER_FREQUENCY; 112 } 113 114 void bl2_plat_runtime_setup(void) 115 { 116 return; 117 } 118