1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <platform_def.h> 28 #include <plat_imx8.h> 29 30 static const mmap_region_t imx_mmap[] = { 31 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0}, 32 }; 33 34 static const struct aipstz_cfg aipstz[] = { 35 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 36 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 37 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {0}, 40 }; 41 42 static const struct imx_rdc_cfg rdc[] = { 43 /* Master domain assignment */ 44 RDC_MDAn(RDC_MDA_M7, DID1), 45 46 /* peripherals domain permission */ 47 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 48 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 49 50 /* memory region */ 51 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 52 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 53 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 54 55 /* Sentinel */ 56 {0}, 57 }; 58 59 static entry_point_info_t bl32_image_ep_info; 60 static entry_point_info_t bl33_image_ep_info; 61 62 /* get SPSR for BL33 entry */ 63 static uint32_t get_spsr_for_bl33_entry(void) 64 { 65 unsigned long el_status; 66 unsigned long mode; 67 uint32_t spsr; 68 69 /* figure out what mode we enter the non-secure world */ 70 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 71 el_status &= ID_AA64PFR0_ELX_MASK; 72 73 mode = (el_status) ? MODE_EL2 : MODE_EL1; 74 75 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 76 return spsr; 77 } 78 79 static void bl31_tzc380_setup(void) 80 { 81 unsigned int val; 82 83 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 84 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 85 return; 86 87 tzc380_init(IMX_TZASC_BASE); 88 89 /* 90 * Need to substact offset 0x40000000 from CPU address when 91 * programming tzasc region for i.mx8mn. 92 */ 93 94 /* Enable 1G-5G S/NS RW */ 95 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 96 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 97 } 98 99 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 100 u_register_t arg2, u_register_t arg3) 101 { 102 static console_t console; 103 int i; 104 105 /* Enable CSU NS access permission */ 106 for (i = 0; i < 64; i++) { 107 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 108 } 109 110 imx_aipstz_init(aipstz); 111 112 imx_rdc_init(rdc); 113 114 imx8m_caam_init(); 115 116 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 117 IMX_CONSOLE_BAUDRATE, &console); 118 /* This console is only used for boot stage */ 119 console_set_scope(&console, CONSOLE_FLAG_BOOT); 120 121 /* 122 * tell BL3-1 where the non-secure software image is located 123 * and the entry state information. 124 */ 125 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 126 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 127 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 128 129 #ifdef SPD_opteed 130 /* Populate entry point information for BL32 */ 131 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 132 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 133 bl32_image_ep_info.pc = BL32_BASE; 134 bl32_image_ep_info.spsr = 0; 135 136 /* Pass TEE base and size to bl33 */ 137 bl33_image_ep_info.args.arg1 = BL32_BASE; 138 bl33_image_ep_info.args.arg2 = BL32_SIZE; 139 #endif 140 141 bl31_tzc380_setup(); 142 } 143 144 void bl31_plat_arch_setup(void) 145 { 146 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 147 MT_MEMORY | MT_RW | MT_SECURE); 148 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 149 MT_MEMORY | MT_RO | MT_SECURE); 150 #if USE_COHERENT_MEM 151 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 152 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 153 MT_DEVICE | MT_RW | MT_SECURE); 154 #endif 155 mmap_add(imx_mmap); 156 157 init_xlat_tables(); 158 159 enable_mmu_el3(0); 160 } 161 162 void bl31_platform_setup(void) 163 { 164 generic_delay_timer_init(); 165 166 /* select the CKIL source to 32K OSC */ 167 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 168 169 plat_gic_driver_init(); 170 plat_gic_init(); 171 172 imx_gpc_init(); 173 } 174 175 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 176 { 177 if (type == NON_SECURE) 178 return &bl33_image_ep_info; 179 if (type == SECURE) 180 return &bl32_image_ep_info; 181 182 return NULL; 183 } 184 185 unsigned int plat_get_syscnt_freq2(void) 186 { 187 return COUNTER_FREQUENCY; 188 } 189