1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_csu.h> 29 #include <platform_def.h> 30 #include <plat_imx8.h> 31 32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 33 34 static const mmap_region_t imx_mmap[] = { 35 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 36 CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP, 37 {0}, 38 }; 39 40 static const struct aipstz_cfg aipstz[] = { 41 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {0}, 46 }; 47 48 static const struct imx_rdc_cfg rdc[] = { 49 /* Master domain assignment */ 50 RDC_MDAn(RDC_MDA_M7, DID1), 51 52 /* peripherals domain permission */ 53 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 54 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 55 56 /* memory region */ 57 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 58 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 59 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 60 61 /* Sentinel */ 62 {0}, 63 }; 64 65 static const struct imx_csu_cfg csu_cfg[] = { 66 /* peripherals csl setting */ 67 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 68 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 69 70 /* master HP0~1 */ 71 72 /* SA setting */ 73 74 /* HP control setting */ 75 76 /* Sentinel */ 77 {0} 78 }; 79 80 81 static entry_point_info_t bl32_image_ep_info; 82 static entry_point_info_t bl33_image_ep_info; 83 84 /* get SPSR for BL33 entry */ 85 static uint32_t get_spsr_for_bl33_entry(void) 86 { 87 unsigned long el_status; 88 unsigned long mode; 89 uint32_t spsr; 90 91 /* figure out what mode we enter the non-secure world */ 92 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 93 el_status &= ID_AA64PFR0_ELX_MASK; 94 95 mode = (el_status) ? MODE_EL2 : MODE_EL1; 96 97 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 98 return spsr; 99 } 100 101 static void bl31_tzc380_setup(void) 102 { 103 unsigned int val; 104 105 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 106 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 107 return; 108 109 tzc380_init(IMX_TZASC_BASE); 110 111 /* 112 * Need to substact offset 0x40000000 from CPU address when 113 * programming tzasc region for i.mx8mn. 114 */ 115 116 /* Enable 1G-5G S/NS RW */ 117 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 118 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 119 } 120 121 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 122 u_register_t arg2, u_register_t arg3) 123 { 124 static console_t console; 125 unsigned int val; 126 int i; 127 128 /* Enable CSU NS access permission */ 129 for (i = 0; i < 64; i++) { 130 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 131 } 132 133 imx_aipstz_init(aipstz); 134 135 imx_rdc_init(rdc); 136 137 imx_csu_init(csu_cfg); 138 139 /* config the ocram memory range for secure access */ 140 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); 141 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 142 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 143 144 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 145 IMX_CONSOLE_BAUDRATE, &console); 146 /* This console is only used for boot stage */ 147 console_set_scope(&console, CONSOLE_FLAG_BOOT); 148 149 imx8m_caam_init(); 150 151 /* 152 * tell BL3-1 where the non-secure software image is located 153 * and the entry state information. 154 */ 155 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 156 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 157 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 158 159 #if defined(SPD_opteed) || defined(SPD_trusty) 160 /* Populate entry point information for BL32 */ 161 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 162 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 163 bl32_image_ep_info.pc = BL32_BASE; 164 bl32_image_ep_info.spsr = 0; 165 166 /* Pass TEE base and size to bl33 */ 167 bl33_image_ep_info.args.arg1 = BL32_BASE; 168 bl33_image_ep_info.args.arg2 = BL32_SIZE; 169 170 #ifdef SPD_trusty 171 bl32_image_ep_info.args.arg0 = BL32_SIZE; 172 bl32_image_ep_info.args.arg1 = BL32_BASE; 173 #else 174 /* Make sure memory is clean */ 175 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 176 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 177 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 178 #endif 179 #endif 180 181 bl31_tzc380_setup(); 182 } 183 184 #define MAP_BL31_TOTAL \ 185 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 186 #define MAP_BL31_RO \ 187 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 188 #define MAP_COHERENT_MEM \ 189 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 190 MT_DEVICE | MT_RW | MT_SECURE) 191 #define MAP_BL32_TOTAL \ 192 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 193 194 void bl31_plat_arch_setup(void) 195 { 196 const mmap_region_t bl_regions[] = { 197 MAP_BL31_TOTAL, 198 MAP_BL31_RO, 199 #if USE_COHERENT_MEM 200 MAP_COHERENT_MEM, 201 #endif 202 /* Map TEE memory */ 203 MAP_BL32_TOTAL, 204 {0} 205 }; 206 207 setup_page_tables(bl_regions, imx_mmap); 208 enable_mmu_el3(0); 209 } 210 211 void bl31_platform_setup(void) 212 { 213 generic_delay_timer_init(); 214 215 /* select the CKIL source to 32K OSC */ 216 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 217 218 /* Init the dram info */ 219 dram_info_init(SAVED_DRAM_TIMING_BASE); 220 221 plat_gic_driver_init(); 222 plat_gic_init(); 223 224 imx_gpc_init(); 225 } 226 227 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 228 { 229 if (type == NON_SECURE) 230 return &bl33_image_ep_info; 231 if (type == SECURE) 232 return &bl32_image_ep_info; 233 234 return NULL; 235 } 236 237 unsigned int plat_get_syscnt_freq2(void) 238 { 239 return COUNTER_FREQUENCY; 240 } 241 242 #ifdef SPD_trusty 243 void plat_trusty_set_boot_args(aapcs64_params_t *args) 244 { 245 args->arg0 = BL32_SIZE; 246 args->arg1 = BL32_BASE; 247 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 248 } 249 #endif 250