1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_csu.h> 29 #include <platform_def.h> 30 #include <plat_imx8.h> 31 32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 33 34 static const mmap_region_t imx_mmap[] = { 35 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0}, 36 }; 37 38 static const struct aipstz_cfg aipstz[] = { 39 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {0}, 44 }; 45 46 static const struct imx_rdc_cfg rdc[] = { 47 /* Master domain assignment */ 48 RDC_MDAn(RDC_MDA_M7, DID1), 49 50 /* peripherals domain permission */ 51 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 52 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 53 54 /* memory region */ 55 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 56 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 57 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 58 59 /* Sentinel */ 60 {0}, 61 }; 62 63 static const struct imx_csu_cfg csu_cfg[] = { 64 /* peripherals csl setting */ 65 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 66 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 67 68 /* master HP0~1 */ 69 70 /* SA setting */ 71 72 /* HP control setting */ 73 74 /* Sentinel */ 75 {0} 76 }; 77 78 79 static entry_point_info_t bl32_image_ep_info; 80 static entry_point_info_t bl33_image_ep_info; 81 82 /* get SPSR for BL33 entry */ 83 static uint32_t get_spsr_for_bl33_entry(void) 84 { 85 unsigned long el_status; 86 unsigned long mode; 87 uint32_t spsr; 88 89 /* figure out what mode we enter the non-secure world */ 90 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 91 el_status &= ID_AA64PFR0_ELX_MASK; 92 93 mode = (el_status) ? MODE_EL2 : MODE_EL1; 94 95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 96 return spsr; 97 } 98 99 static void bl31_tzc380_setup(void) 100 { 101 unsigned int val; 102 103 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 104 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 105 return; 106 107 tzc380_init(IMX_TZASC_BASE); 108 109 /* 110 * Need to substact offset 0x40000000 from CPU address when 111 * programming tzasc region for i.mx8mn. 112 */ 113 114 /* Enable 1G-5G S/NS RW */ 115 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 116 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 117 } 118 119 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 120 u_register_t arg2, u_register_t arg3) 121 { 122 static console_t console; 123 unsigned int val; 124 int i; 125 126 /* Enable CSU NS access permission */ 127 for (i = 0; i < 64; i++) { 128 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 129 } 130 131 imx_aipstz_init(aipstz); 132 133 imx_rdc_init(rdc); 134 135 imx_csu_init(csu_cfg); 136 137 /* config the ocram memory range for secure access */ 138 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); 139 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 140 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 141 142 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 143 IMX_CONSOLE_BAUDRATE, &console); 144 /* This console is only used for boot stage */ 145 console_set_scope(&console, CONSOLE_FLAG_BOOT); 146 147 imx8m_caam_init(); 148 149 /* 150 * tell BL3-1 where the non-secure software image is located 151 * and the entry state information. 152 */ 153 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 154 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 155 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 156 157 #if defined(SPD_opteed) || defined(SPD_trusty) 158 /* Populate entry point information for BL32 */ 159 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 160 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 161 bl32_image_ep_info.pc = BL32_BASE; 162 bl32_image_ep_info.spsr = 0; 163 164 /* Pass TEE base and size to bl33 */ 165 bl33_image_ep_info.args.arg1 = BL32_BASE; 166 bl33_image_ep_info.args.arg2 = BL32_SIZE; 167 168 #ifdef SPD_trusty 169 bl32_image_ep_info.args.arg0 = BL32_SIZE; 170 bl32_image_ep_info.args.arg1 = BL32_BASE; 171 #else 172 /* Make sure memory is clean */ 173 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 174 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 175 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 176 #endif 177 #endif 178 179 bl31_tzc380_setup(); 180 } 181 182 void bl31_plat_arch_setup(void) 183 { 184 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 185 MT_MEMORY | MT_RW | MT_SECURE); 186 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 187 MT_MEMORY | MT_RO | MT_SECURE); 188 #if USE_COHERENT_MEM 189 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 190 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 191 MT_DEVICE | MT_RW | MT_SECURE); 192 #endif 193 194 /* Map TEE memory */ 195 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 196 197 mmap_add(imx_mmap); 198 199 init_xlat_tables(); 200 201 enable_mmu_el3(0); 202 } 203 204 void bl31_platform_setup(void) 205 { 206 generic_delay_timer_init(); 207 208 /* select the CKIL source to 32K OSC */ 209 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 210 211 /* Init the dram info */ 212 dram_info_init(SAVED_DRAM_TIMING_BASE); 213 214 plat_gic_driver_init(); 215 plat_gic_init(); 216 217 imx_gpc_init(); 218 } 219 220 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 221 { 222 if (type == NON_SECURE) 223 return &bl33_image_ep_info; 224 if (type == SECURE) 225 return &bl32_image_ep_info; 226 227 return NULL; 228 } 229 230 unsigned int plat_get_syscnt_freq2(void) 231 { 232 return COUNTER_FREQUENCY; 233 } 234 235 #ifdef SPD_trusty 236 void plat_trusty_set_boot_args(aapcs64_params_t *args) 237 { 238 args->arg0 = BL32_SIZE; 239 args->arg1 = BL32_BASE; 240 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 241 } 242 #endif 243