1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_common.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 static const mmap_region_t imx_mmap[] = { 38 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 39 CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP, 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static struct imx_rdc_cfg rdc[] = { 52 /* Master domain assignment */ 53 RDC_MDAn(RDC_MDA_M7, DID1), 54 55 /* peripherals domain permission */ 56 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 57 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 58 59 /* memory region */ 60 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 61 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 62 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 63 64 /* Sentinel */ 65 {0}, 66 }; 67 68 static const struct imx_csu_cfg csu_cfg[] = { 69 /* peripherals csl setting */ 70 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 71 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 72 73 /* master HP0~1 */ 74 75 /* SA setting */ 76 77 /* HP control setting */ 78 79 /* Sentinel */ 80 {0} 81 }; 82 83 84 static entry_point_info_t bl32_image_ep_info; 85 static entry_point_info_t bl33_image_ep_info; 86 87 /* get SPSR for BL33 entry */ 88 static uint32_t get_spsr_for_bl33_entry(void) 89 { 90 unsigned long el_status; 91 unsigned long mode; 92 uint32_t spsr; 93 94 /* figure out what mode we enter the non-secure world */ 95 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 96 el_status &= ID_AA64PFR0_ELX_MASK; 97 98 mode = (el_status) ? MODE_EL2 : MODE_EL1; 99 100 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 101 return spsr; 102 } 103 104 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 105 u_register_t arg2, u_register_t arg3) 106 { 107 unsigned int console_base = IMX_BOOT_UART_BASE; 108 static console_t console; 109 unsigned int val; 110 int i, ret; 111 112 /* Enable CSU NS access permission */ 113 for (i = 0; i < 64; i++) { 114 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 115 } 116 117 imx_aipstz_init(aipstz); 118 119 if (console_base == 0U) { 120 console_base = imx8m_uart_get_base(); 121 } 122 123 imx_rdc_init(rdc, console_base); 124 125 imx_csu_init(csu_cfg); 126 127 /* 128 * Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes 129 * partial write issue. The AXI2AHB bridge is used for masters that access the TCM 130 * through system bus. Please refer to errata ERR050362 for more information. 131 */ 132 mmio_setbits_32((GPV5_BASE_ADDR + FORCE_INCR_OFFSET), FORCE_INCR_BIT_MASK); 133 134 /* config the ocram memory range for secure access */ 135 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); 136 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 137 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 138 139 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 140 IMX_CONSOLE_BAUDRATE, &console); 141 /* This console is only used for boot stage */ 142 console_set_scope(&console, CONSOLE_FLAG_BOOT); 143 144 imx8m_caam_init(); 145 146 /* 147 * tell BL3-1 where the non-secure software image is located 148 * and the entry state information. 149 */ 150 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 151 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 152 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 153 154 #if defined(SPD_opteed) || defined(SPD_trusty) 155 /* Populate entry point information for BL32 */ 156 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 157 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 158 bl32_image_ep_info.pc = BL32_BASE; 159 bl32_image_ep_info.spsr = 0; 160 161 /* Pass TEE base and size to bl33 */ 162 bl33_image_ep_info.args.arg1 = BL32_BASE; 163 bl33_image_ep_info.args.arg2 = BL32_SIZE; 164 165 #ifdef SPD_trusty 166 bl32_image_ep_info.args.arg0 = BL32_SIZE; 167 bl32_image_ep_info.args.arg1 = BL32_BASE; 168 #else 169 /* Make sure memory is clean */ 170 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 171 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 172 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 173 #endif 174 #endif 175 176 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 177 &bl32_image_ep_info, &bl33_image_ep_info); 178 if (ret != 0) { 179 imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 180 &bl32_image_ep_info, &bl33_image_ep_info); 181 } 182 183 #if !defined(SPD_opteed) && !defined(SPD_trusty) 184 enable_snvs_privileged_access(); 185 #endif 186 } 187 188 #define MAP_BL31_TOTAL \ 189 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 190 #define MAP_BL31_RO \ 191 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 192 #define MAP_COHERENT_MEM \ 193 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 194 MT_DEVICE | MT_RW | MT_SECURE) 195 #define MAP_BL32_TOTAL \ 196 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 197 198 void bl31_plat_arch_setup(void) 199 { 200 const mmap_region_t bl_regions[] = { 201 MAP_BL31_TOTAL, 202 MAP_BL31_RO, 203 #if USE_COHERENT_MEM 204 MAP_COHERENT_MEM, 205 #endif 206 #if defined(SPD_opteed) || defined(SPD_trusty) 207 /* Map TEE memory */ 208 MAP_BL32_TOTAL, 209 #endif 210 {0} 211 }; 212 213 setup_page_tables(bl_regions, imx_mmap); 214 enable_mmu_el3(0); 215 } 216 217 void bl31_platform_setup(void) 218 { 219 generic_delay_timer_init(); 220 221 /* select the CKIL source to 32K OSC */ 222 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 223 224 /* Init the dram info */ 225 dram_info_init(SAVED_DRAM_TIMING_BASE); 226 227 plat_gic_driver_init(); 228 plat_gic_init(); 229 230 imx_gpc_init(); 231 } 232 233 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 234 { 235 if (type == NON_SECURE) 236 return &bl33_image_ep_info; 237 if (type == SECURE) 238 return &bl32_image_ep_info; 239 240 return NULL; 241 } 242 243 unsigned int plat_get_syscnt_freq2(void) 244 { 245 return COUNTER_FREQUENCY; 246 } 247 248 #ifdef SPD_trusty 249 void plat_trusty_set_boot_args(aapcs64_params_t *args) 250 { 251 args->arg0 = BL32_SIZE; 252 args->arg1 = BL32_BASE; 253 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 254 } 255 #endif 256