1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <imx8m_csu.h> 28 #include <platform_def.h> 29 #include <plat_imx8.h> 30 31 static const mmap_region_t imx_mmap[] = { 32 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0}, 33 }; 34 35 static const struct aipstz_cfg aipstz[] = { 36 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 37 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {0}, 41 }; 42 43 static const struct imx_rdc_cfg rdc[] = { 44 /* Master domain assignment */ 45 RDC_MDAn(RDC_MDA_M7, DID1), 46 47 /* peripherals domain permission */ 48 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 49 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 50 51 /* memory region */ 52 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 53 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 54 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 55 56 /* Sentinel */ 57 {0}, 58 }; 59 60 static const struct imx_csu_cfg csu_cfg[] = { 61 /* peripherals csl setting */ 62 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 63 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 64 65 /* master HP0~1 */ 66 67 /* SA setting */ 68 69 /* HP control setting */ 70 71 /* Sentinel */ 72 {0} 73 }; 74 75 76 static entry_point_info_t bl32_image_ep_info; 77 static entry_point_info_t bl33_image_ep_info; 78 79 /* get SPSR for BL33 entry */ 80 static uint32_t get_spsr_for_bl33_entry(void) 81 { 82 unsigned long el_status; 83 unsigned long mode; 84 uint32_t spsr; 85 86 /* figure out what mode we enter the non-secure world */ 87 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 88 el_status &= ID_AA64PFR0_ELX_MASK; 89 90 mode = (el_status) ? MODE_EL2 : MODE_EL1; 91 92 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 93 return spsr; 94 } 95 96 static void bl31_tzc380_setup(void) 97 { 98 unsigned int val; 99 100 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 101 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 102 return; 103 104 tzc380_init(IMX_TZASC_BASE); 105 106 /* 107 * Need to substact offset 0x40000000 from CPU address when 108 * programming tzasc region for i.mx8mn. 109 */ 110 111 /* Enable 1G-5G S/NS RW */ 112 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 113 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 114 } 115 116 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 117 u_register_t arg2, u_register_t arg3) 118 { 119 static console_t console; 120 int i; 121 122 /* Enable CSU NS access permission */ 123 for (i = 0; i < 64; i++) { 124 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 125 } 126 127 imx_aipstz_init(aipstz); 128 129 imx_rdc_init(rdc); 130 131 imx_csu_init(csu_cfg); 132 133 /* config the ocram memory range for secure access */ 134 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0xc1); 135 136 imx8m_caam_init(); 137 138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 139 IMX_CONSOLE_BAUDRATE, &console); 140 /* This console is only used for boot stage */ 141 console_set_scope(&console, CONSOLE_FLAG_BOOT); 142 143 /* 144 * tell BL3-1 where the non-secure software image is located 145 * and the entry state information. 146 */ 147 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 148 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 #ifdef SPD_opteed 152 /* Populate entry point information for BL32 */ 153 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 154 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 155 bl32_image_ep_info.pc = BL32_BASE; 156 bl32_image_ep_info.spsr = 0; 157 158 /* Pass TEE base and size to bl33 */ 159 bl33_image_ep_info.args.arg1 = BL32_BASE; 160 bl33_image_ep_info.args.arg2 = BL32_SIZE; 161 #endif 162 163 bl31_tzc380_setup(); 164 } 165 166 void bl31_plat_arch_setup(void) 167 { 168 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 169 MT_MEMORY | MT_RW | MT_SECURE); 170 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 171 MT_MEMORY | MT_RO | MT_SECURE); 172 #if USE_COHERENT_MEM 173 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 174 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 175 MT_DEVICE | MT_RW | MT_SECURE); 176 #endif 177 mmap_add(imx_mmap); 178 179 init_xlat_tables(); 180 181 enable_mmu_el3(0); 182 } 183 184 void bl31_platform_setup(void) 185 { 186 generic_delay_timer_init(); 187 188 /* select the CKIL source to 32K OSC */ 189 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 190 191 plat_gic_driver_init(); 192 plat_gic_init(); 193 194 imx_gpc_init(); 195 } 196 197 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 198 { 199 if (type == NON_SECURE) 200 return &bl33_image_ep_info; 201 if (type == SECURE) 202 return &bl32_image_ep_info; 203 204 return NULL; 205 } 206 207 unsigned int plat_get_syscnt_freq2(void) 208 { 209 return COUNTER_FREQUENCY; 210 } 211