1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <stdlib.h> 10 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <lib/smccc.h> 16 #include <services/std_svc.h> 17 18 #include <gpc.h> 19 #include <imx_sip_svc.h> 20 #include <platform_def.h> 21 22 #define CCGR(x) (0x4000 + (x) * 0x10) 23 24 #define MIPI_PWR_REQ BIT(0) 25 #define OTG1_PWR_REQ BIT(2) 26 #define HSIOMIX_PWR_REQ BIT(4) 27 #define GPUMIX_PWR_REQ BIT(7) 28 #define DISPMIX_PWR_REQ BIT(10) 29 30 #define HSIOMIX_ADB400_SYNC BIT(5) 31 #define DISPMIX_ADB400_SYNC BIT(7) 32 #define GPUMIX_ADB400_SYNC (0x5 << 9) 33 #define HSIOMIX_ADB400_ACK BIT(23) 34 #define DISPMIX_ADB400_ACK BIT(25) 35 #define GPUMIX_ADB400_ACK (0x5 << 27) 36 37 #define MIPI_PGC 0xc00 38 #define OTG1_PGC 0xc80 39 #define HSIOMIX_PGC 0xd00 40 #define GPUMIX_PGC 0xdc0 41 #define DISPMIX_PGC 0xe80 42 43 enum pu_domain_id { 44 HSIOMIX, 45 OTG1 = 2, 46 GPUMIX = 4, 47 DISPMIX = 9, 48 MIPI, 49 }; 50 51 /* PU domain, add some hole to minimize the uboot change */ 52 static struct imx_pwr_domain pu_domains[11] = { 53 [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false), 54 [OTG1] = IMX_PD_DOMAIN(OTG1, true), 55 [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false), 56 [DISPMIX] = IMX_MIX_DOMAIN(DISPMIX, false), 57 [MIPI] = IMX_PD_DOMAIN(MIPI, true), 58 }; 59 60 static unsigned int pu_domain_status; 61 62 void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) 63 { 64 if (domain_id > MIPI) { 65 return; 66 } 67 68 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; 69 70 if (on) { 71 if (pwr_domain->need_sync) { 72 pu_domain_status |= (1 << domain_id); 73 } 74 75 /* HSIOMIX has no PU bit, so skip for it */ 76 if (domain_id != HSIOMIX) { 77 /* clear the PGC bit */ 78 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); 79 80 /* power up the domain */ 81 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); 82 83 /* wait for power request done */ 84 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { 85 ; 86 } 87 } 88 89 if (domain_id == DISPMIX) { 90 /* de-reset bus_blk clk and 91 * enable bus_blk clk 92 */ 93 mmio_write_32(0x32e28000, 0x100); 94 mmio_write_32(0x32e28004, 0x100); 95 } 96 97 /* handle the ADB400 sync */ 98 if (pwr_domain->need_sync) { 99 /* clear adb power down request */ 100 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); 101 102 /* wait for adb power request ack */ 103 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { 104 ; 105 } 106 } 107 } else { 108 pu_domain_status &= ~(1 << domain_id); 109 110 if (domain_id == OTG1) { 111 return; 112 } 113 114 /* handle the ADB400 sync */ 115 if (pwr_domain->need_sync) { 116 117 /* set adb power down request */ 118 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); 119 120 /* wait for adb power request ack */ 121 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { 122 ; 123 } 124 } 125 126 /* HSIOMIX has no PU bit, so skip for it */ 127 if (domain_id != HSIOMIX) { 128 /* set the PGC bit */ 129 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); 130 131 /* power down the domain */ 132 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); 133 134 /* wait for power request done */ 135 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { 136 ; 137 } 138 } 139 } 140 } 141 142 void imx_gpc_init(void) 143 { 144 unsigned int val; 145 int i; 146 147 /* mask all the wakeup irq by default */ 148 for (i = 0; i < 4; i++) { 149 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); 150 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); 151 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); 152 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); 153 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); 154 } 155 156 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 157 /* use GIC wake_request to wakeup C0~C3 from LPM */ 158 val |= CORE_WKUP_FROM_GIC; 159 /* clear the MASTER0 LPM handshake */ 160 val &= ~MASTER0_LPM_HSK; 161 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 162 163 /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ 164 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | 165 MASTER2_MAPPING)); 166 167 /* set all mix/PU in A53 domain */ 168 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); 169 170 /* 171 * Set the CORE & SCU power up timing: 172 * SW = 0x1, SW2ISO = 0x1; 173 * the CPU CORE and SCU power up timming counter 174 * is drived by 32K OSC, each domain's power up 175 * latency is (SW + SW2ISO) / 32768 176 */ 177 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); 178 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); 179 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); 180 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401); 181 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); 182 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, 183 (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT)); 184 185 /* set DUMMY PDN/PUP ACK by default for A53 domain */ 186 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 187 A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); 188 189 /* clear DSM by default */ 190 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 191 val &= ~SLPCR_EN_DSM; 192 /* enable the fast wakeup wait mode */ 193 val |= SLPCR_A53_FASTWUP_WAIT_MODE; 194 /* clear the RBC */ 195 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); 196 /* set the STBY_COUNT to 0x5, (128 * 30)us */ 197 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); 198 val |= (0x5 << SLPCR_STBY_COUNT_SHFT); 199 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 200 201 /* 202 * USB PHY power up needs to make sure RESET bit in SRC is clear, 203 * otherwise, the PU power up bit in GPC will NOT self-cleared. 204 * only need to do it once. 205 */ 206 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); 207 } 208