1 /* 2 * Copyright 2019-2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <stdlib.h> 10 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <lib/smccc.h> 16 #include <services/std_svc.h> 17 18 #include <gpc.h> 19 #include <imx_sip_svc.h> 20 #include <platform_def.h> 21 22 #define CCGR(x) (0x4000 + (x) * 0x10) 23 24 void imx_gpc_init(void) 25 { 26 unsigned int val; 27 int i; 28 29 /* mask all the wakeup irq by default */ 30 for (i = 0; i < 4; i++) { 31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); 32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); 33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); 34 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); 35 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); 36 } 37 38 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 39 /* use GIC wake_request to wakeup C0~C3 from LPM */ 40 val |= CORE_WKUP_FROM_GIC; 41 /* clear the MASTER0 LPM handshake */ 42 val &= ~MASTER0_LPM_HSK; 43 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 44 45 /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ 46 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | 47 MASTER2_MAPPING)); 48 49 /* set all mix/PU in A53 domain */ 50 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); 51 52 /* 53 * Set the CORE & SCU power up timing: 54 * SW = 0x1, SW2ISO = 0x1; 55 * the CPU CORE and SCU power up timming counter 56 * is drived by 32K OSC, each domain's power up 57 * latency is (SW + SW2ISO) / 32768 58 */ 59 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); 60 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); 61 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); 62 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401); 63 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); 64 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, 65 (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT)); 66 67 /* set DUMMY PDN/PUP ACK by default for A53 domain */ 68 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 69 A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); 70 71 /* clear DSM by default */ 72 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 73 val &= ~SLPCR_EN_DSM; 74 /* enable the fast wakeup wait mode */ 75 val |= SLPCR_A53_FASTWUP_WAIT_MODE; 76 /* clear the RBC */ 77 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); 78 /* set the STBY_COUNT to 0x5, (128 * 30)us */ 79 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); 80 val |= (0x5 << SLPCR_STBY_COUNT_SHFT); 81 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 82 83 /* 84 * USB PHY power up needs to make sure RESET bit in SRC is clear, 85 * otherwise, the PU power up bit in GPC will NOT self-cleared. 86 * only need to do it once. 87 */ 88 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); 89 90 /* enable all the power domain by default */ 91 for (i = 0; i < 103; i++) 92 mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3); 93 mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x485); 94 } 95