1*58fdd608SJacky Bai /* 2*58fdd608SJacky Bai * Copyright 2019-2020 NXP 3*58fdd608SJacky Bai * 4*58fdd608SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*58fdd608SJacky Bai */ 6*58fdd608SJacky Bai 7*58fdd608SJacky Bai #include <stdbool.h> 8*58fdd608SJacky Bai #include <stdint.h> 9*58fdd608SJacky Bai #include <stdlib.h> 10*58fdd608SJacky Bai 11*58fdd608SJacky Bai #include <common/debug.h> 12*58fdd608SJacky Bai #include <drivers/delay_timer.h> 13*58fdd608SJacky Bai #include <lib/mmio.h> 14*58fdd608SJacky Bai #include <lib/psci/psci.h> 15*58fdd608SJacky Bai #include <lib/smccc.h> 16*58fdd608SJacky Bai #include <services/std_svc.h> 17*58fdd608SJacky Bai 18*58fdd608SJacky Bai #include <gpc.h> 19*58fdd608SJacky Bai #include <imx_sip_svc.h> 20*58fdd608SJacky Bai #include <platform_def.h> 21*58fdd608SJacky Bai 22*58fdd608SJacky Bai #define CCGR(x) (0x4000 + (x) * 0x10) 23*58fdd608SJacky Bai 24*58fdd608SJacky Bai void imx_gpc_init(void) 25*58fdd608SJacky Bai { 26*58fdd608SJacky Bai unsigned int val; 27*58fdd608SJacky Bai int i; 28*58fdd608SJacky Bai 29*58fdd608SJacky Bai /* mask all the wakeup irq by default */ 30*58fdd608SJacky Bai for (i = 0; i < 4; i++) { 31*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); 32*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); 33*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); 34*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); 35*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); 36*58fdd608SJacky Bai } 37*58fdd608SJacky Bai 38*58fdd608SJacky Bai val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 39*58fdd608SJacky Bai /* use GIC wake_request to wakeup C0~C3 from LPM */ 40*58fdd608SJacky Bai val |= CORE_WKUP_FROM_GIC; 41*58fdd608SJacky Bai /* clear the MASTER0 LPM handshake */ 42*58fdd608SJacky Bai val &= ~MASTER0_LPM_HSK; 43*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 44*58fdd608SJacky Bai 45*58fdd608SJacky Bai /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ 46*58fdd608SJacky Bai mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | 47*58fdd608SJacky Bai MASTER2_MAPPING)); 48*58fdd608SJacky Bai 49*58fdd608SJacky Bai /* set all mix/PU in A53 domain */ 50*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); 51*58fdd608SJacky Bai 52*58fdd608SJacky Bai /* 53*58fdd608SJacky Bai * Set the CORE & SCU power up timing: 54*58fdd608SJacky Bai * SW = 0x1, SW2ISO = 0x1; 55*58fdd608SJacky Bai * the CPU CORE and SCU power up timming counter 56*58fdd608SJacky Bai * is drived by 32K OSC, each domain's power up 57*58fdd608SJacky Bai * latency is (SW + SW2ISO) / 32768 58*58fdd608SJacky Bai */ 59*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); 60*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); 61*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); 62*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401); 63*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); 64*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, 65*58fdd608SJacky Bai (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT)); 66*58fdd608SJacky Bai 67*58fdd608SJacky Bai /* set DUMMY PDN/PUP ACK by default for A53 domain */ 68*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 69*58fdd608SJacky Bai A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); 70*58fdd608SJacky Bai 71*58fdd608SJacky Bai /* clear DSM by default */ 72*58fdd608SJacky Bai val = mmio_read_32(IMX_GPC_BASE + SLPCR); 73*58fdd608SJacky Bai val &= ~SLPCR_EN_DSM; 74*58fdd608SJacky Bai /* enable the fast wakeup wait mode */ 75*58fdd608SJacky Bai val |= SLPCR_A53_FASTWUP_WAIT_MODE; 76*58fdd608SJacky Bai /* clear the RBC */ 77*58fdd608SJacky Bai val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); 78*58fdd608SJacky Bai /* set the STBY_COUNT to 0x5, (128 * 30)us */ 79*58fdd608SJacky Bai val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); 80*58fdd608SJacky Bai val |= (0x5 << SLPCR_STBY_COUNT_SHFT); 81*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + SLPCR, val); 82*58fdd608SJacky Bai 83*58fdd608SJacky Bai /* 84*58fdd608SJacky Bai * USB PHY power up needs to make sure RESET bit in SRC is clear, 85*58fdd608SJacky Bai * otherwise, the PU power up bit in GPC will NOT self-cleared. 86*58fdd608SJacky Bai * only need to do it once. 87*58fdd608SJacky Bai */ 88*58fdd608SJacky Bai mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); 89*58fdd608SJacky Bai 90*58fdd608SJacky Bai /* enable all the power domain by default */ 91*58fdd608SJacky Bai for (i = 0; i < 103; i++) 92*58fdd608SJacky Bai mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3); 93*58fdd608SJacky Bai mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x485); 94*58fdd608SJacky Bai } 95