1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 8 #define PLATFORM_LINKER_ARCH aarch64 9 10 #define PLATFORM_STACK_SIZE 0xB00 11 #define CACHE_WRITEBACK_GRANULE 64 12 13 #define PLAT_PRIMARY_CPU 0x0 14 #define PLATFORM_MAX_CPU_PER_CLUSTER 4 15 #define PLATFORM_CLUSTER_COUNT 1 16 #define PLATFORM_CLUSTER0_CORE_COUNT 4 17 #define PLATFORM_CLUSTER1_CORE_COUNT 0 18 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 19 20 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 21 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 22 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 23 24 #define PWR_DOMAIN_AT_MAX_LVL U(1) 25 #define PLAT_MAX_PWR_LVL U(2) 26 #define PLAT_MAX_OFF_STATE U(4) 27 #define PLAT_MAX_RET_STATE U(2) 28 29 #define PLAT_WAIT_RET_STATE U(1) 30 #define PLAT_STOP_OFF_STATE U(3) 31 32 #define BL31_BASE U(0x920000) 33 #define BL31_LIMIT U(0x940000) 34 #define BL32_BASE U(0xbe000000) 35 36 /* non-secure uboot base */ 37 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 38 39 /* GICv3 base address */ 40 #define PLAT_GICD_BASE U(0x38800000) 41 #define PLAT_GICR_BASE U(0x38880000) 42 43 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 44 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 45 46 #define MAX_XLAT_TABLES 8 47 #define MAX_MMAP_REGIONS 16 48 49 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ 50 51 #define IMX_BOOT_UART_BASE U(0x30890000) 52 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 53 54 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 55 #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 56 #define IMX_CONSOLE_BAUDRATE 115200 57 58 #define IMX_AIPSTZ1 U(0x301f0000) 59 #define IMX_AIPSTZ2 U(0x305f0000) 60 #define IMX_AIPSTZ3 U(0x309f0000) 61 #define IMX_AIPSTZ4 U(0x32df0000) 62 63 #define IMX_AIPS_BASE U(0x30000000) 64 #define IMX_AIPS_SIZE U(0xC00000) 65 #define IMX_GPV_BASE U(0x32000000) 66 #define IMX_GPV_SIZE U(0x800000) 67 #define IMX_AIPS1_BASE U(0x30200000) 68 #define IMX_AIPS4_BASE U(0x32c00000) 69 #define IMX_ANAMIX_BASE U(0x30360000) 70 #define IMX_CCM_BASE U(0x30380000) 71 #define IMX_SRC_BASE U(0x30390000) 72 #define IMX_GPC_BASE U(0x303a0000) 73 #define IMX_RDC_BASE U(0x303d0000) 74 #define IMX_CSU_BASE U(0x303e0000) 75 #define IMX_WDOG_BASE U(0x30280000) 76 #define IMX_SNVS_BASE U(0x30370000) 77 #define IMX_NOC_BASE U(0x32700000) 78 #define IMX_TZASC_BASE U(0x32F80000) 79 #define IMX_IOMUX_GPR_BASE U(0x30340000) 80 #define IMX_DDRC_BASE U(0x3d400000) 81 #define IMX_DDRPHY_BASE U(0x3c000000) 82 #define IMX_DDR_IPS_BASE U(0x3d000000) 83 #define IMX_ROM_BASE U(0x0) 84 85 #define GPV_BASE U(0x32000000) 86 #define GPV_SIZE U(0x800000) 87 #define IMX_GIC_BASE PLAT_GICD_BASE 88 #define IMX_GIC_SIZE U(0x200000) 89 90 #define WDOG_WSR U(0x2) 91 #define WDOG_WCR_WDZST BIT(0) 92 #define WDOG_WCR_WDBG BIT(1) 93 #define WDOG_WCR_WDE BIT(2) 94 #define WDOG_WCR_WDT BIT(3) 95 #define WDOG_WCR_SRS BIT(4) 96 #define WDOG_WCR_WDA BIT(5) 97 #define WDOG_WCR_SRE BIT(6) 98 #define WDOG_WCR_WDW BIT(7) 99 100 #define SRC_A53RCR0 U(0x4) 101 #define SRC_A53RCR1 U(0x8) 102 #define SRC_OTG1PHY_SCR U(0x20) 103 #define SRC_OTG2PHY_SCR U(0x24) 104 #define SRC_GPR1_OFFSET U(0x74) 105 106 #define SNVS_LPCR U(0x38) 107 #define SNVS_LPCR_SRTC_ENV BIT(0) 108 #define SNVS_LPCR_DP_EN BIT(5) 109 #define SNVS_LPCR_TOP BIT(6) 110 111 #define IOMUXC_GPR10 U(0x28) 112 #define GPR_TZASC_EN BIT(0) 113 #define GPR_TZASC_EN_LOCK BIT(16) 114 115 #define ANAMIX_MISC_CTL U(0x124) 116 117 #define MAX_CSU_NUM U(64) 118 119 #define OCRAM_S_BASE U(0x00180000) 120 #define OCRAM_S_SIZE U(0x8000) 121 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 122 123 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 124 125 #define IMX_WDOG_B_RESET 126