1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <common/tbbr/tbbr_img_def.h> 9 #include <lib/utils_def.h> 10 11 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 12 #define PLATFORM_LINKER_ARCH aarch64 13 14 #define PLATFORM_STACK_SIZE 0xB00 15 #define CACHE_WRITEBACK_GRANULE 64 16 17 #define PLAT_PRIMARY_CPU U(0x0) 18 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 19 #define PLATFORM_CLUSTER_COUNT U(1) 20 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 21 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 22 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 23 24 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 25 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 26 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 27 28 #define PWR_DOMAIN_AT_MAX_LVL U(1) 29 #define PLAT_MAX_PWR_LVL U(2) 30 #define PLAT_MAX_OFF_STATE U(4) 31 #define PLAT_MAX_RET_STATE U(2) 32 33 #define PLAT_WAIT_RET_STATE U(1) 34 #define PLAT_STOP_OFF_STATE U(3) 35 36 #define PLAT_PRI_BITS U(3) 37 #define PLAT_SDEI_CRITICAL_PRI 0x10 38 #define PLAT_SDEI_NORMAL_PRI 0x20 39 #define PLAT_SDEI_SGI_PRIVATE U(9) 40 41 #if defined(NEED_BL2) 42 #define BL2_BASE U(0x920000) 43 #define BL2_LIMIT U(0x940000) 44 #define BL31_BASE U(0x900000) 45 #define BL31_LIMIT U(0x920000) 46 #define IMX_FIP_BASE U(0x40310000) 47 #define IMX_FIP_SIZE U(0x000300000) 48 #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) 49 50 /* Define FIP image location on eMMC */ 51 #define IMX_FIP_MMC_BASE U(0x100000) 52 53 #define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */ 54 #else 55 #define BL31_BASE U(0x920000) 56 #define BL31_LIMIT U(0x940000) 57 #endif 58 59 /* non-secure uboot base */ 60 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 61 #define PLAT_NS_IMAGE_SIZE U(0x00200000) 62 63 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 64 65 /* GICv3 base address */ 66 #define PLAT_GICD_BASE U(0x38800000) 67 #define PLAT_GICR_BASE U(0x38880000) 68 69 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 70 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 71 72 #define MAX_XLAT_TABLES 8 73 #define MAX_MMAP_REGIONS 16 74 75 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ 76 77 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 78 79 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 80 #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 81 #define IMX_CONSOLE_BAUDRATE 115200 82 83 #define IMX_AIPSTZ1 U(0x301f0000) 84 #define IMX_AIPSTZ2 U(0x305f0000) 85 #define IMX_AIPSTZ3 U(0x309f0000) 86 #define IMX_AIPSTZ4 U(0x32df0000) 87 88 #define IMX_AIPS_BASE U(0x30000000) 89 #define IMX_AIPS_SIZE U(0x3000000) 90 #define IMX_GPV_BASE U(0x32000000) 91 #define IMX_GPV_SIZE U(0x800000) 92 #define IMX_AIPS1_BASE U(0x30200000) 93 #define IMX_AIPS4_BASE U(0x32c00000) 94 #define IMX_ANAMIX_BASE U(0x30360000) 95 #define IMX_CCM_BASE U(0x30380000) 96 #define IMX_SRC_BASE U(0x30390000) 97 #define IMX_GPC_BASE U(0x303a0000) 98 #define IMX_RDC_BASE U(0x303d0000) 99 #define IMX_CSU_BASE U(0x303e0000) 100 #define IMX_WDOG_BASE U(0x30280000) 101 #define IMX_SNVS_BASE U(0x30370000) 102 #define IMX_NOC_BASE U(0x32700000) 103 #define IMX_TZASC_BASE U(0x32F80000) 104 #define IMX_IOMUX_GPR_BASE U(0x30340000) 105 #define IMX_CAAM_BASE U(0x30900000) 106 #define IMX_DDRC_BASE U(0x3d400000) 107 #define IMX_DDRPHY_BASE U(0x3c000000) 108 #define IMX_DDR_IPS_BASE U(0x3d000000) 109 #define IMX_DDR_IPS_SIZE U(0x1800000) 110 #define IMX_ROM_BASE U(0x0) 111 #define IMX_VPUMIX_BASE U(0x38330000) 112 #define IMX_VPUMIX_SIZE U(0x100000) 113 114 #define GPV_BASE U(0x32000000) 115 #define GPV_SIZE U(0x800000) 116 #define IMX_GIC_BASE PLAT_GICD_BASE 117 #define IMX_GIC_SIZE U(0x200000) 118 119 #define WDOG_WSR U(0x2) 120 #define WDOG_WCR_WDZST BIT(0) 121 #define WDOG_WCR_WDBG BIT(1) 122 #define WDOG_WCR_WDE BIT(2) 123 #define WDOG_WCR_WDT BIT(3) 124 #define WDOG_WCR_SRS BIT(4) 125 #define WDOG_WCR_WDA BIT(5) 126 #define WDOG_WCR_SRE BIT(6) 127 #define WDOG_WCR_WDW BIT(7) 128 129 #define SRC_A53RCR0 U(0x4) 130 #define SRC_A53RCR1 U(0x8) 131 #define SRC_OTG1PHY_SCR U(0x20) 132 #define SRC_OTG2PHY_SCR U(0x24) 133 #define SRC_GPR1_OFFSET U(0x74) 134 #define SRC_GPR10_OFFSET U(0x98) 135 #define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 136 137 #define SNVS_LPCR U(0x38) 138 #define SNVS_LPCR_SRTC_ENV BIT(0) 139 #define SNVS_LPCR_DP_EN BIT(5) 140 #define SNVS_LPCR_TOP BIT(6) 141 142 #define IOMUXC_GPR10 U(0x28) 143 #define GPR_TZASC_EN BIT(0) 144 #define GPR_TZASC_EN_LOCK BIT(16) 145 146 #define ANAMIX_MISC_CTL U(0x124) 147 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) 148 149 #define MAX_CSU_NUM U(64) 150 151 #define OCRAM_S_BASE U(0x00180000) 152 #define OCRAM_S_SIZE U(0x8000) 153 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 154 #define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE 155 156 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 157 158 #define IMX_WDOG_B_RESET 159 160 #define MAX_IO_HANDLES 3U 161 #define MAX_IO_DEVICES 2U 162 #define MAX_IO_BLOCK_DEVICES 1U 163 164 #define PLAT_IMX8M_DTO_BASE 0x53000000 165 #define PLAT_IMX8M_DTO_MAX_SIZE 0x1000 166 #define PLAT_IMX_EVENT_LOG_MAX_SIZE UL(0x400) 167