1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_uart.h> 26 #include <plat_imx8.h> 27 28 static const mmap_region_t imx_mmap[] = { 29 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 30 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 31 {0}, 32 }; 33 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 /* get SPSR for BL33 entry */ 38 static uint32_t get_spsr_for_bl33_entry(void) 39 { 40 unsigned long el_status; 41 unsigned long mode; 42 uint32_t spsr; 43 44 /* figure out what mode we enter the non-secure world */ 45 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 46 el_status &= ID_AA64PFR0_ELX_MASK; 47 48 mode = (el_status) ? MODE_EL2 : MODE_EL1; 49 50 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 51 return spsr; 52 } 53 54 void bl31_tzc380_setup(void) 55 { 56 unsigned int val; 57 58 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 59 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 60 return; 61 62 tzc380_init(IMX_TZASC_BASE); 63 64 /* 65 * Need to substact offset 0x40000000 from CPU address when 66 * programming tzasc region for i.mx8mm. 67 */ 68 69 /* Enable 1G-5G S/NS RW */ 70 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 71 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 72 } 73 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 static console_uart_t console; 78 int i; 79 80 /* Enable CSU NS access permission */ 81 for (i = 0; i < 64; i++) { 82 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 83 } 84 85 86 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 87 IMX_CONSOLE_BAUDRATE, &console); 88 /* This console is only used for boot stage */ 89 console_set_scope(&console.console, CONSOLE_FLAG_BOOT); 90 91 /* 92 * tell BL3-1 where the non-secure software image is located 93 * and the entry state information. 94 */ 95 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 96 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 97 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 98 99 bl31_tzc380_setup(); 100 } 101 102 void bl31_plat_arch_setup(void) 103 { 104 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 105 MT_MEMORY | MT_RW | MT_SECURE); 106 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 107 MT_MEMORY | MT_RO | MT_SECURE); 108 #if USE_COHERENT_MEM 109 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 110 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 111 MT_DEVICE | MT_RW | MT_SECURE); 112 #endif 113 mmap_add(imx_mmap); 114 115 init_xlat_tables(); 116 117 enable_mmu_el3(0); 118 } 119 120 void bl31_platform_setup(void) 121 { 122 generic_delay_timer_init(); 123 124 /* select the CKIL source to 32K OSC */ 125 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 126 127 plat_gic_driver_init(); 128 plat_gic_init(); 129 130 imx_gpc_init(); 131 } 132 133 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 134 { 135 if (type == NON_SECURE) 136 return &bl33_image_ep_info; 137 if (type == SECURE) 138 return &bl32_image_ep_info; 139 140 return NULL; 141 } 142 143 unsigned int plat_get_syscnt_freq2(void) 144 { 145 return COUNTER_FREQUENCY; 146 } 147