1*179f82a2SJacky Bai /* 2*179f82a2SJacky Bai * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*179f82a2SJacky Bai * 4*179f82a2SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*179f82a2SJacky Bai */ 6*179f82a2SJacky Bai 7*179f82a2SJacky Bai #include <stdlib.h> 8*179f82a2SJacky Bai #include <stdint.h> 9*179f82a2SJacky Bai #include <stdbool.h> 10*179f82a2SJacky Bai 11*179f82a2SJacky Bai #include <common/debug.h> 12*179f82a2SJacky Bai #include <drivers/delay_timer.h> 13*179f82a2SJacky Bai #include <lib/mmio.h> 14*179f82a2SJacky Bai #include <lib/psci/psci.h> 15*179f82a2SJacky Bai #include <lib/smccc.h> 16*179f82a2SJacky Bai #include <platform_def.h> 17*179f82a2SJacky Bai #include <services/std_svc.h> 18*179f82a2SJacky Bai 19*179f82a2SJacky Bai #include <gpc.h> 20*179f82a2SJacky Bai #include <imx_sip_svc.h> 21*179f82a2SJacky Bai 22*179f82a2SJacky Bai void imx_gpc_init(void) 23*179f82a2SJacky Bai { 24*179f82a2SJacky Bai unsigned int val; 25*179f82a2SJacky Bai int i; 26*179f82a2SJacky Bai 27*179f82a2SJacky Bai /* mask all the wakeup irq by default */ 28*179f82a2SJacky Bai for (i = 0; i < 4; i++) { 29*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); 30*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); 31*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); 32*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); 33*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); 34*179f82a2SJacky Bai } 35*179f82a2SJacky Bai 36*179f82a2SJacky Bai val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 37*179f82a2SJacky Bai /* use GIC wake_request to wakeup C0~C3 from LPM */ 38*179f82a2SJacky Bai val |= 0x30c00000; 39*179f82a2SJacky Bai /* clear the MASTER0 LPM handshake */ 40*179f82a2SJacky Bai val &= ~(1 << 6); 41*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 42*179f82a2SJacky Bai 43*179f82a2SJacky Bai /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ 44*179f82a2SJacky Bai mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | 45*179f82a2SJacky Bai MASTER2_MAPPING)); 46*179f82a2SJacky Bai 47*179f82a2SJacky Bai /* set all mix/PU in A53 domain */ 48*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); 49*179f82a2SJacky Bai 50*179f82a2SJacky Bai /* 51*179f82a2SJacky Bai * Set the CORE & SCU power up timing: 52*179f82a2SJacky Bai * SW = 0x1, SW2ISO = 0x1; 53*179f82a2SJacky Bai * the CPU CORE and SCU power up timming counter 54*179f82a2SJacky Bai * is drived by 32K OSC, each domain's power up 55*179f82a2SJacky Bai * latency is (SW + SW2ISO) / 32768 56*179f82a2SJacky Bai */ 57*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81); 58*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81); 59*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81); 60*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81); 61*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81); 62*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, 63*179f82a2SJacky Bai (0x59 << 10) | 0x5B | (0x2 << 20)); 64*179f82a2SJacky Bai 65*179f82a2SJacky Bai /* set DUMMY PDN/PUP ACK by default for A53 domain */ 66*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 67*179f82a2SJacky Bai A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); 68*179f82a2SJacky Bai 69*179f82a2SJacky Bai /* clear DSM by default */ 70*179f82a2SJacky Bai val = mmio_read_32(IMX_GPC_BASE + SLPCR); 71*179f82a2SJacky Bai val &= ~SLPCR_EN_DSM; 72*179f82a2SJacky Bai /* enable the fast wakeup wait mode */ 73*179f82a2SJacky Bai val |= SLPCR_A53_FASTWUP_WAIT_MODE; 74*179f82a2SJacky Bai /* clear the RBC */ 75*179f82a2SJacky Bai val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); 76*179f82a2SJacky Bai /* set the STBY_COUNT to 0x5, (128 * 30)us */ 77*179f82a2SJacky Bai val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); 78*179f82a2SJacky Bai val |= (0x5 << SLPCR_STBY_COUNT_SHFT); 79*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + SLPCR, val); 80*179f82a2SJacky Bai 81*179f82a2SJacky Bai /* 82*179f82a2SJacky Bai * USB PHY power up needs to make sure RESET bit in SRC is clear, 83*179f82a2SJacky Bai * otherwise, the PU power up bit in GPC will NOT self-cleared. 84*179f82a2SJacky Bai * only need to do it once. 85*179f82a2SJacky Bai */ 86*179f82a2SJacky Bai mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); 87*179f82a2SJacky Bai mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); 88*179f82a2SJacky Bai 89*179f82a2SJacky Bai /* enable all the power domain by default */ 90*179f82a2SJacky Bai mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf); 91*179f82a2SJacky Bai } 92