1*8d150c95SMarco Felsch /* 2*8d150c95SMarco Felsch * Copyright 2022-2023 NXP 3*8d150c95SMarco Felsch * 4*8d150c95SMarco Felsch * SPDX-License-Identifier: BSD-3-Clause 5*8d150c95SMarco Felsch */ 6*8d150c95SMarco Felsch 7*8d150c95SMarco Felsch #include <lib/mmio.h> 8*8d150c95SMarco Felsch #include <platform_def.h> 9*8d150c95SMarco Felsch 10*8d150c95SMarco Felsch #define SNVS_HPCOMR U(0x04) 11*8d150c95SMarco Felsch #define SNVS_NPSWA_EN BIT(31) 12*8d150c95SMarco Felsch enable_snvs_privileged_access(void)13*8d150c95SMarco Felschvoid enable_snvs_privileged_access(void) 14*8d150c95SMarco Felsch { 15*8d150c95SMarco Felsch unsigned int val; 16*8d150c95SMarco Felsch 17*8d150c95SMarco Felsch val = mmio_read_32(IMX_SNVS_BASE + SNVS_HPCOMR); 18*8d150c95SMarco Felsch mmio_write_32(IMX_SNVS_BASE + SNVS_HPCOMR, val | SNVS_NPSWA_EN); 19*8d150c95SMarco Felsch } 20