1 /* 2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <dram.h> 17 #include <gpc.h> 18 #include <imx8m_psci.h> 19 #include <plat_imx8.h> 20 21 /* 22 * below callback functions need to be override by i.mx8mq, 23 * for other i.mx8m soc, if no special requirement, 24 * reuse below ones. 25 */ 26 #pragma weak imx_validate_power_state 27 #pragma weak imx_pwr_domain_off 28 #pragma weak imx_domain_suspend 29 #pragma weak imx_domain_suspend_finish 30 #pragma weak imx_get_sys_suspend_power_state 31 32 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 33 { 34 /* The non-secure entrypoint should be in RAM space */ 35 if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET) 36 return PSCI_E_INVALID_PARAMS; 37 38 return PSCI_E_SUCCESS; 39 } 40 41 int imx_pwr_domain_on(u_register_t mpidr) 42 { 43 unsigned int core_id; 44 uint64_t base_addr = BL31_START; 45 46 core_id = MPIDR_AFFLVL0_VAL(mpidr); 47 48 imx_set_cpu_secure_entry(core_id, base_addr); 49 imx_set_cpu_pwr_on(core_id); 50 51 return PSCI_E_SUCCESS; 52 } 53 54 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 55 { 56 plat_gic_pcpu_init(); 57 plat_gic_cpuif_enable(); 58 } 59 60 void imx_pwr_domain_off(const psci_power_state_t *target_state) 61 { 62 uint64_t mpidr = read_mpidr_el1(); 63 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 64 65 plat_gic_cpuif_disable(); 66 imx_set_cpu_pwr_off(core_id); 67 } 68 69 int imx_validate_power_state(unsigned int power_state, 70 psci_power_state_t *req_state) 71 { 72 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 73 int pwr_type = psci_get_pstate_type(power_state); 74 int state_id = psci_get_pstate_id(power_state); 75 76 if (pwr_lvl > PLAT_MAX_PWR_LVL) 77 return PSCI_E_INVALID_PARAMS; 78 79 if (pwr_type == PSTATE_TYPE_STANDBY) { 80 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 81 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 82 } 83 84 if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { 85 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; 86 CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE; 87 } 88 89 return PSCI_E_SUCCESS; 90 } 91 92 void imx_cpu_standby(plat_local_state_t cpu_state) 93 { 94 dsb(); 95 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 96 isb(); 97 98 wfi(); 99 100 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 101 isb(); 102 } 103 104 void imx_domain_suspend(const psci_power_state_t *target_state) 105 { 106 uint64_t base_addr = BL31_START; 107 uint64_t mpidr = read_mpidr_el1(); 108 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 109 110 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 111 plat_gic_cpuif_disable(); 112 imx_set_cpu_secure_entry(core_id, base_addr); 113 imx_set_cpu_lpm(core_id, true); 114 } else { 115 dsb(); 116 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 117 isb(); 118 } 119 120 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) 121 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); 122 123 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { 124 imx_set_sys_lpm(core_id, true); 125 dram_enter_retention(); 126 imx_anamix_override(true); 127 } 128 } 129 130 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 131 { 132 uint64_t mpidr = read_mpidr_el1(); 133 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 134 135 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { 136 imx_anamix_override(false); 137 dram_exit_retention(); 138 imx_set_sys_lpm(core_id, false); 139 } 140 141 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { 142 imx_clear_rbc_count(); 143 imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN); 144 } 145 146 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 147 imx_set_cpu_lpm(core_id, false); 148 plat_gic_cpuif_enable(); 149 } else { 150 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 151 isb(); 152 } 153 } 154 155 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 156 { 157 unsigned int i; 158 159 for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 160 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; 161 } 162 163 static void __dead2 imx_wdog_restart(bool external_reset) 164 { 165 uintptr_t wdog_base = IMX_WDOG_BASE; 166 unsigned int val; 167 168 val = mmio_read_16(wdog_base); 169 /* 170 * Common watchdog init flags, for additional details check 171 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR) 172 * 173 * Initial bit selection: 174 * WDOG_WCR_WDE - Enable the watchdog. 175 * 176 * 0x000E mask is used to keep previous values (that could be set 177 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits). 178 */ 179 val = (val & 0x000E) | WDOG_WCR_WDE; 180 if (external_reset) { 181 /* 182 * To assert WDOG_B (external reset) we have 183 * to set WDA bit 0 (already set in previous step). 184 * SRS bits are required to be set to 1 (no effect on the 185 * system). 186 */ 187 val |= WDOG_WCR_SRS; 188 } else { 189 /* 190 * To assert Software Reset Signal (internal reset) we have 191 * to set SRS bit to 0 (already set in previous step). 192 * SRE bit is required to be set to 1 when used in 193 * conjunction with the Software Reset Signal before 194 * SRS asserton, otherwise SRS bit will just automatically 195 * reset to 1. 196 * 197 * Also we set WDA to 1 (no effect on system). 198 */ 199 val |= WDOG_WCR_SRE | WDOG_WCR_WDA; 200 } 201 202 mmio_write_16(wdog_base, val); 203 204 mmio_write_16(wdog_base + WDOG_WSR, 0x5555); 205 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa); 206 while (1) 207 ; 208 } 209 210 void __dead2 imx_system_reset(void) 211 { 212 #ifdef IMX_WDOG_B_RESET 213 imx_wdog_restart(true); 214 #else 215 imx_wdog_restart(false); 216 #endif 217 } 218 219 int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 220 { 221 imx_wdog_restart(false); 222 223 /* 224 * imx_wdog_restart cannot return (as it's a __dead function), 225 * however imx_system_reset2 has to return some value according 226 * to PSCI v1.1 spec. 227 */ 228 return 0; 229 } 230 231 void __dead2 imx_system_off(void) 232 { 233 uint32_t val; 234 235 val = mmio_read_32(IMX_SNVS_BASE + SNVS_LPCR); 236 val |= SNVS_LPCR_SRTC_ENV | SNVS_LPCR_DP_EN | SNVS_LPCR_TOP; 237 mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, val); 238 239 while (1) 240 ; 241 } 242 243 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 244 { 245 /* 246 * before enter WAIT or STOP mode with PLAT(SCU) power down, 247 * rbc count need to be enabled to make sure PLAT is 248 * power down successfully even if the the wakeup IRQ is pending 249 * early before the power down sequence. the RBC counter is 250 * drived by the 32K OSC, so delay 30us to make sure the counter 251 * is really running. 252 */ 253 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { 254 imx_set_rbc_count(); 255 udelay(30); 256 } 257 258 while (1) 259 wfi(); 260 } 261