1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <dram.h> 17 #include <gpc.h> 18 #include <imx8m_psci.h> 19 #include <plat_imx8.h> 20 21 /* 22 * below callback functions need to be override by i.mx8mq, 23 * for other i.mx8m soc, if no special requirement, 24 * reuse below ones. 25 */ 26 #pragma weak imx_validate_power_state 27 #pragma weak imx_domain_suspend 28 #pragma weak imx_domain_suspend_finish 29 #pragma weak imx_get_sys_suspend_power_state 30 31 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 32 { 33 /* The non-secure entrypoint should be in RAM space */ 34 if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET) 35 return PSCI_E_INVALID_PARAMS; 36 37 return PSCI_E_SUCCESS; 38 } 39 40 int imx_pwr_domain_on(u_register_t mpidr) 41 { 42 unsigned int core_id; 43 uint64_t base_addr = BL31_BASE; 44 45 core_id = MPIDR_AFFLVL0_VAL(mpidr); 46 47 imx_set_cpu_secure_entry(core_id, base_addr); 48 imx_set_cpu_pwr_on(core_id); 49 50 return PSCI_E_SUCCESS; 51 } 52 53 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 54 { 55 plat_gic_pcpu_init(); 56 plat_gic_cpuif_enable(); 57 } 58 59 void imx_pwr_domain_off(const psci_power_state_t *target_state) 60 { 61 uint64_t mpidr = read_mpidr_el1(); 62 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 63 64 plat_gic_cpuif_disable(); 65 imx_set_cpu_pwr_off(core_id); 66 } 67 68 int imx_validate_power_state(unsigned int power_state, 69 psci_power_state_t *req_state) 70 { 71 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 72 int pwr_type = psci_get_pstate_type(power_state); 73 int state_id = psci_get_pstate_id(power_state); 74 75 if (pwr_lvl > PLAT_MAX_PWR_LVL) 76 return PSCI_E_INVALID_PARAMS; 77 78 if (pwr_type == PSTATE_TYPE_STANDBY) { 79 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 80 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 81 } 82 83 if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { 84 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; 85 CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE; 86 } 87 88 return PSCI_E_SUCCESS; 89 } 90 91 void imx_cpu_standby(plat_local_state_t cpu_state) 92 { 93 dsb(); 94 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 95 isb(); 96 97 wfi(); 98 99 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 100 isb(); 101 } 102 103 void imx_domain_suspend(const psci_power_state_t *target_state) 104 { 105 uint64_t base_addr = BL31_BASE; 106 uint64_t mpidr = read_mpidr_el1(); 107 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 108 109 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 110 plat_gic_cpuif_disable(); 111 imx_set_cpu_secure_entry(core_id, base_addr); 112 imx_set_cpu_lpm(core_id, true); 113 } else { 114 dsb(); 115 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 116 isb(); 117 } 118 119 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) 120 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); 121 122 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { 123 imx_set_sys_lpm(core_id, true); 124 dram_enter_retention(); 125 } 126 } 127 128 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 129 { 130 uint64_t mpidr = read_mpidr_el1(); 131 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 132 133 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { 134 dram_exit_retention(); 135 imx_set_sys_lpm(core_id, false); 136 } 137 138 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { 139 imx_clear_rbc_count(); 140 imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN); 141 } 142 143 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 144 imx_set_cpu_lpm(core_id, false); 145 plat_gic_cpuif_enable(); 146 } else { 147 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 148 isb(); 149 } 150 } 151 152 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 153 { 154 unsigned int i; 155 156 for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 157 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; 158 } 159 160 static void __dead2 imx_wdog_restart(bool external_reset) 161 { 162 uintptr_t wdog_base = IMX_WDOG_BASE; 163 unsigned int val; 164 165 val = mmio_read_16(wdog_base); 166 /* 167 * Common watchdog init flags, for additional details check 168 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR) 169 * 170 * Initial bit selection: 171 * WDOG_WCR_WDE - Enable the watchdog. 172 * 173 * 0x000E mask is used to keep previous values (that could be set 174 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits). 175 */ 176 val = (val & 0x000E) | WDOG_WCR_WDE; 177 if (external_reset) { 178 /* 179 * To assert WDOG_B (external reset) we have 180 * to set WDA bit 0 (already set in previous step). 181 * SRS bits are required to be set to 1 (no effect on the 182 * system). 183 */ 184 val |= WDOG_WCR_SRS; 185 } else { 186 /* 187 * To assert Software Reset Signal (internal reset) we have 188 * to set SRS bit to 0 (already set in previous step). 189 * SRE bit is required to be set to 1 when used in 190 * conjunction with the Software Reset Signal before 191 * SRS asserton, otherwise SRS bit will just automatically 192 * reset to 1. 193 * 194 * Also we set WDA to 1 (no effect on system). 195 */ 196 val |= WDOG_WCR_SRE | WDOG_WCR_WDA; 197 } 198 199 mmio_write_16(wdog_base, val); 200 201 mmio_write_16(wdog_base + WDOG_WSR, 0x5555); 202 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa); 203 while (1) 204 ; 205 } 206 207 void __dead2 imx_system_reset(void) 208 { 209 #ifdef IMX_WDOG_B_RESET 210 imx_wdog_restart(true); 211 #else 212 imx_wdog_restart(false); 213 #endif 214 } 215 216 int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 217 { 218 imx_wdog_restart(false); 219 220 /* 221 * imx_wdog_restart cannot return (as it's a __dead function), 222 * however imx_system_reset2 has to return some value according 223 * to PSCI v1.1 spec. 224 */ 225 return 0; 226 } 227 228 void __dead2 imx_system_off(void) 229 { 230 mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV | 231 SNVS_LPCR_DP_EN | SNVS_LPCR_TOP); 232 233 while (1) 234 ; 235 } 236 237 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 238 { 239 /* 240 * before enter WAIT or STOP mode with PLAT(SCU) power down, 241 * rbc count need to be enabled to make sure PLAT is 242 * power down successfully even if the the wakeup IRQ is pending 243 * early before the power down sequence. the RBC counter is 244 * drived by the 32K OSC, so delay 30us to make sure the counter 245 * is really running. 246 */ 247 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { 248 imx_set_rbc_count(); 249 udelay(30); 250 } 251 252 while (1) 253 wfi(); 254 } 255