1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <gpc.h> 17 #include <imx8m_psci.h> 18 #include <plat_imx8.h> 19 20 /* 21 * below callback functions need to be override by i.mx8mq, 22 * for other i.mx8m soc, if no special requirement, 23 * reuse below ones. 24 */ 25 #pragma weak imx_validate_power_state 26 #pragma weak imx_domain_suspend 27 #pragma weak imx_domain_suspend_finish 28 #pragma weak imx_get_sys_suspend_power_state 29 30 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 31 { 32 /* The non-secure entrypoint should be in RAM space */ 33 if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET) 34 return PSCI_E_INVALID_PARAMS; 35 36 return PSCI_E_SUCCESS; 37 } 38 39 int imx_pwr_domain_on(u_register_t mpidr) 40 { 41 unsigned int core_id; 42 uint64_t base_addr = BL31_BASE; 43 44 core_id = MPIDR_AFFLVL0_VAL(mpidr); 45 46 imx_set_cpu_secure_entry(core_id, base_addr); 47 imx_set_cpu_pwr_on(core_id); 48 49 return PSCI_E_SUCCESS; 50 } 51 52 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 53 { 54 plat_gic_pcpu_init(); 55 plat_gic_cpuif_enable(); 56 } 57 58 void imx_pwr_domain_off(const psci_power_state_t *target_state) 59 { 60 uint64_t mpidr = read_mpidr_el1(); 61 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 62 63 plat_gic_cpuif_disable(); 64 imx_set_cpu_pwr_off(core_id); 65 } 66 67 int imx_validate_power_state(unsigned int power_state, 68 psci_power_state_t *req_state) 69 { 70 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 71 int pwr_type = psci_get_pstate_type(power_state); 72 int state_id = psci_get_pstate_id(power_state); 73 74 if (pwr_lvl > PLAT_MAX_PWR_LVL) 75 return PSCI_E_INVALID_PARAMS; 76 77 if (pwr_type == PSTATE_TYPE_STANDBY) { 78 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 79 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 80 } 81 82 if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { 83 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; 84 CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE; 85 } 86 87 return PSCI_E_SUCCESS; 88 } 89 90 void imx_cpu_standby(plat_local_state_t cpu_state) 91 { 92 dsb(); 93 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 94 isb(); 95 96 wfi(); 97 98 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 99 isb(); 100 } 101 102 void imx_domain_suspend(const psci_power_state_t *target_state) 103 { 104 uint64_t base_addr = BL31_BASE; 105 uint64_t mpidr = read_mpidr_el1(); 106 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 107 108 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 109 plat_gic_cpuif_disable(); 110 imx_set_cpu_secure_entry(core_id, base_addr); 111 imx_set_cpu_lpm(core_id, true); 112 } else { 113 dsb(); 114 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 115 isb(); 116 } 117 118 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) 119 imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); 120 121 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) 122 imx_set_sys_lpm(core_id, true); 123 } 124 125 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 126 { 127 uint64_t mpidr = read_mpidr_el1(); 128 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 129 130 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) 131 imx_set_sys_lpm(core_id, false); 132 133 if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { 134 imx_clear_rbc_count(); 135 imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN); 136 } 137 138 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 139 imx_set_cpu_lpm(core_id, false); 140 plat_gic_cpuif_enable(); 141 } else { 142 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 143 isb(); 144 } 145 } 146 147 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 148 { 149 unsigned int i; 150 151 for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 152 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; 153 } 154 155 static void __dead2 imx_wdog_restart(bool external_reset) 156 { 157 uintptr_t wdog_base = IMX_WDOG_BASE; 158 unsigned int val; 159 160 val = mmio_read_16(wdog_base); 161 /* 162 * Common watchdog init flags, for additional details check 163 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR) 164 * 165 * Initial bit selection: 166 * WDOG_WCR_WDE - Enable the watchdog. 167 * 168 * 0x000E mask is used to keep previous values (that could be set 169 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits). 170 */ 171 val = (val & 0x000E) | WDOG_WCR_WDE; 172 if (external_reset) { 173 /* 174 * To assert WDOG_B (external reset) we have 175 * to set WDA bit 0 (already set in previous step). 176 * SRS bits are required to be set to 1 (no effect on the 177 * system). 178 */ 179 val |= WDOG_WCR_SRS; 180 } else { 181 /* 182 * To assert Software Reset Signal (internal reset) we have 183 * to set SRS bit to 0 (already set in previous step). 184 * SRE bit is required to be set to 1 when used in 185 * conjunction with the Software Reset Signal before 186 * SRS asserton, otherwise SRS bit will just automatically 187 * reset to 1. 188 * 189 * Also we set WDA to 1 (no effect on system). 190 */ 191 val |= WDOG_WCR_SRE | WDOG_WCR_WDA; 192 } 193 194 mmio_write_16(wdog_base, val); 195 196 mmio_write_16(wdog_base + WDOG_WSR, 0x5555); 197 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa); 198 while (1) 199 ; 200 } 201 202 void __dead2 imx_system_reset(void) 203 { 204 #ifdef IMX_WDOG_B_RESET 205 imx_wdog_restart(true); 206 #else 207 imx_wdog_restart(false); 208 #endif 209 } 210 211 int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 212 { 213 imx_wdog_restart(false); 214 215 /* 216 * imx_wdog_restart cannot return (as it's a __dead function), 217 * however imx_system_reset2 has to return some value according 218 * to PSCI v1.1 spec. 219 */ 220 return 0; 221 } 222 223 void __dead2 imx_system_off(void) 224 { 225 mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV | 226 SNVS_LPCR_DP_EN | SNVS_LPCR_TOP); 227 228 while (1) 229 ; 230 } 231 232 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 233 { 234 /* 235 * before enter WAIT or STOP mode with PLAT(SCU) power down, 236 * rbc count need to be enabled to make sure PLAT is 237 * power down successfully even if the the wakeup IRQ is pending 238 * early before the power down sequence. the RBC counter is 239 * drived by the 32K OSC, so delay 30us to make sure the counter 240 * is really running. 241 */ 242 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { 243 imx_set_rbc_count(); 244 udelay(30); 245 } 246 247 while (1) 248 wfi(); 249 } 250