1 /* 2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <gpc.h> 17 #include <imx8m_psci.h> 18 #include <plat_imx8.h> 19 20 #define MAX_PLL_NUM U(10) 21 22 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; 23 24 DEFINE_BAKERY_LOCK(gpc_lock); 25 26 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 27 28 #pragma weak imx_set_cpu_pwr_off 29 #pragma weak imx_set_cpu_pwr_on 30 #pragma weak imx_set_cpu_lpm 31 #pragma weak imx_set_cluster_powerdown 32 #pragma weak imx_set_sys_wakeup 33 #pragma weak imx_noc_slot_config 34 #pragma weak imx_gpc_handler 35 #pragma weak imx_anamix_override 36 37 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) 38 { 39 uint64_t temp_base; 40 41 temp_base = (uint64_t) sec_entrypoint; 42 temp_base >>= 2; 43 44 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), 45 ((uint32_t)(temp_base >> 22) & 0xffff)); 46 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, 47 ((uint32_t)temp_base & 0x003fffff)); 48 } 49 50 void imx_set_cpu_pwr_off(unsigned int core_id) 51 { 52 53 bakery_lock_get(&gpc_lock); 54 55 /* enable the wfi power down of the core */ 56 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 57 58 bakery_lock_release(&gpc_lock); 59 60 /* assert the pcg pcr bit of the core */ 61 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 62 } 63 64 void imx_set_cpu_pwr_on(unsigned int core_id) 65 { 66 bakery_lock_get(&gpc_lock); 67 68 /* clear the wfi power down bit of the core */ 69 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 70 71 bakery_lock_release(&gpc_lock); 72 73 /* assert the ncpuporeset */ 74 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 75 /* assert the pcg pcr bit of the core */ 76 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 77 /* sw power up the core */ 78 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); 79 80 /* wait for the power up finished */ 81 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) 82 ; 83 84 /* deassert the pcg pcr bit of the core */ 85 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 86 /* deassert the ncpuporeset */ 87 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 88 } 89 90 void imx_set_cpu_lpm(unsigned int core_id, bool pdn) 91 { 92 bakery_lock_get(&gpc_lock); 93 94 if (pdn) { 95 /* enable the core WFI PDN & IRQ PUP */ 96 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 97 COREx_IRQ_WUP(core_id)); 98 /* assert the pcg pcr bit of the core */ 99 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 100 } else { 101 /* disbale CORE WFI PDN & IRQ PUP */ 102 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 103 COREx_IRQ_WUP(core_id)); 104 /* deassert the pcg pcr bit of the core */ 105 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 106 } 107 108 bakery_lock_release(&gpc_lock); 109 } 110 111 /* 112 * the plat and noc can only be power up & down by slot method, 113 * slot0: plat power down; slot1: noc power down; slot2: noc power up; 114 * slot3: plat power up. plat's pup&pdn ack is used by default. if 115 * noc is config to power down, then noc's pdn ack should be used. 116 */ 117 static void imx_a53_plat_slot_config(bool pdn) 118 { 119 if (pdn) { 120 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 121 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 122 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | 123 A53_PLAT_PUP_ACK); 124 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 125 } else { 126 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 127 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 128 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | 129 A53_DUMMY_PDN_ACK); 130 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 131 } 132 } 133 134 void imx_set_cluster_standby(bool enter) 135 { 136 /* 137 * Enable BIT 6 of A53 AD register to make sure system 138 * don't enter LPM mode. 139 */ 140 if (enter) 141 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 142 else 143 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 144 } 145 146 /* i.mx8mq need to override it */ 147 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) 148 { 149 uint32_t val; 150 151 if (!is_local_state_run(power_state)) { 152 /* config C0~1's LPM, enable a53 clock off in LPM */ 153 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, 154 LPM_MODE(power_state)); 155 /* config C2-3's LPM */ 156 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); 157 158 /* enable PLAT/SCU power down */ 159 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 160 val &= ~EN_L2_WFI_PDN; 161 /* L2 cache memory is on in WAIT mode */ 162 if (is_local_state_off(power_state)) { 163 val |= (L2PGE | EN_PLAT_PDN); 164 imx_a53_plat_slot_config(true); 165 } 166 167 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 168 } else { 169 /* clear the slot and ack for cluster power down */ 170 imx_a53_plat_slot_config(false); 171 /* reverse the cluster level setting */ 172 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); 173 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); 174 175 /* clear PLAT/SCU power down */ 176 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), 177 EN_L2_WFI_PDN); 178 } 179 } 180 181 static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) 182 { 183 unsigned int n = id >> ISENABLER_SHIFT; 184 185 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 186 } 187 188 /* 189 * gic's clock will be gated in system suspend, so gic has no ability to 190 * to wakeup the system, we need to config the imr based on the irq 191 * enable status in gic, then gpc will monitor the wakeup irq 192 */ 193 void imx_set_sys_wakeup(unsigned int last_core, bool pdn) 194 { 195 uint32_t irq_mask; 196 uintptr_t gicd_base = PLAT_GICD_BASE; 197 198 if (pdn) 199 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), 200 IRQ_SRC_A53_WUP); 201 else 202 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, 203 A53_CORE_WUP_SRC(last_core)); 204 205 /* clear last core's IMR based on GIC's mask setting */ 206 for (int i = 0; i < IRQ_IMR_NUM; i++) { 207 if (pdn) 208 /* set the wakeup irq base GIC */ 209 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); 210 else 211 irq_mask = IMR_MASK_ALL; 212 213 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, 214 irq_mask); 215 } 216 } 217 218 /* 219 * this function only need to be override by platform 220 * that support noc power down, for example: imx8mm. 221 * otherwize, keep it empty. 222 */ 223 void imx_noc_slot_config(bool pdn) 224 { 225 226 } 227 228 /* this is common for all imx8m soc */ 229 void imx_set_sys_lpm(unsigned int last_core, bool retention) 230 { 231 uint32_t val; 232 233 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 234 val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 235 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 236 237 if (retention) 238 val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 239 SLPCR_BYPASS_PMIC_READY); 240 241 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 242 243 /* config the noc power down */ 244 imx_noc_slot_config(retention); 245 246 /* config wakeup irqs' mask in gpc */ 247 imx_set_sys_wakeup(last_core, retention); 248 } 249 250 void imx_set_rbc_count(void) 251 { 252 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 253 (0x8 << SLPCR_RBC_COUNT_SHIFT)); 254 } 255 256 void imx_clear_rbc_count(void) 257 { 258 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 259 (0x3f << SLPCR_RBC_COUNT_SHIFT)); 260 } 261 262 struct pll_override pll[MAX_PLL_NUM] = { 263 {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, 264 {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, 265 {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, 266 {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, 267 {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, 268 {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, 269 {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, 270 {.reg = 0x94, .override_mask = 0x5555500, }, 271 {.reg = 0x104, .override_mask = 0x5555500, }, 272 {.reg = 0x114, .override_mask = 0x500, }, 273 }; 274 275 #define PLL_BYPASS BIT(4) 276 void imx_anamix_override(bool enter) 277 { 278 unsigned int i; 279 280 /* 281 * bypass all the plls & enable the override bit before 282 * entering DSM mode. 283 */ 284 for (i = 0U; i < MAX_PLL_NUM; i++) { 285 if (enter) { 286 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 287 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 288 } else { 289 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 290 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 291 } 292 } 293 } 294 295 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) 296 { 297 switch (x1) { 298 case FSL_SIP_CONFIG_GPC_PM_DOMAIN: 299 imx_gpc_pm_domain_enable(x2, x3); 300 break; 301 default: 302 return SMC_UNK; 303 } 304 305 return 0; 306 } 307