1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 15 #include <gpc.h> 16 #include <imx8m_psci.h> 17 #include <plat_imx8.h> 18 19 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; 20 21 DEFINE_BAKERY_LOCK(gpc_lock); 22 23 #pragma weak imx_set_cpu_pwr_off 24 #pragma weak imx_set_cpu_pwr_on 25 #pragma weak imx_set_cpu_lpm 26 #pragma weak imx_set_cluster_powerdown 27 28 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) 29 { 30 uint64_t temp_base; 31 32 temp_base = (uint64_t) sec_entrypoint; 33 temp_base >>= 2; 34 35 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), 36 ((uint32_t)(temp_base >> 22) & 0xffff)); 37 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, 38 ((uint32_t)temp_base & 0x003fffff)); 39 } 40 41 void imx_set_cpu_pwr_off(unsigned int core_id) 42 { 43 44 bakery_lock_get(&gpc_lock); 45 46 /* enable the wfi power down of the core */ 47 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 48 49 bakery_lock_release(&gpc_lock); 50 51 /* assert the pcg pcr bit of the core */ 52 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 53 } 54 55 void imx_set_cpu_pwr_on(unsigned int core_id) 56 { 57 bakery_lock_get(&gpc_lock); 58 59 /* clear the wfi power down bit of the core */ 60 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 61 62 bakery_lock_release(&gpc_lock); 63 64 /* assert the ncpuporeset */ 65 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 66 /* assert the pcg pcr bit of the core */ 67 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 68 /* sw power up the core */ 69 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); 70 71 /* wait for the power up finished */ 72 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) 73 ; 74 75 /* deassert the pcg pcr bit of the core */ 76 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 77 /* deassert the ncpuporeset */ 78 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 79 } 80 81 void imx_set_cpu_lpm(unsigned int core_id, bool pdn) 82 { 83 bakery_lock_get(&gpc_lock); 84 85 if (pdn) { 86 /* enable the core WFI PDN & IRQ PUP */ 87 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 88 COREx_IRQ_WUP(core_id)); 89 /* assert the pcg pcr bit of the core */ 90 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 91 } else { 92 /* disbale CORE WFI PDN & IRQ PUP */ 93 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 94 COREx_IRQ_WUP(core_id)); 95 /* deassert the pcg pcr bit of the core */ 96 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 97 } 98 99 bakery_lock_release(&gpc_lock); 100 } 101 102 /* 103 * the plat and noc can only be power up & down by slot method, 104 * slot0: plat power down; slot1: noc power down; slot2: noc power up; 105 * slot3: plat power up. plat's pup&pdn ack is used by default. if 106 * noc is config to power down, then noc's pdn ack should be used. 107 */ 108 static void imx_a53_plat_slot_config(bool pdn) 109 { 110 if (pdn) { 111 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 112 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 113 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | 114 A53_PLAT_PUP_ACK); 115 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 116 } else { 117 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 118 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 119 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | 120 A53_DUMMY_PDN_ACK); 121 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 122 } 123 } 124 125 void imx_set_cluster_standby(bool enter) 126 { 127 /* 128 * Enable BIT 6 of A53 AD register to make sure system 129 * don't enter LPM mode. 130 */ 131 if (enter) 132 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 133 else 134 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 135 } 136 137 /* i.mx8mq need to override it */ 138 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) 139 { 140 uint32_t val; 141 142 if (!is_local_state_run(power_state)) { 143 /* config C0~1's LPM, enable a53 clock off in LPM */ 144 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, 145 LPM_MODE(power_state)); 146 /* config C2-3's LPM */ 147 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); 148 149 /* enable PLAT/SCU power down */ 150 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 151 val &= ~EN_L2_WFI_PDN; 152 /* L2 cache memory is on in WAIT mode */ 153 if (is_local_state_off(power_state)) { 154 val |= (L2PGE | EN_PLAT_PDN); 155 imx_a53_plat_slot_config(true); 156 } 157 158 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 159 } else { 160 /* clear the slot and ack for cluster power down */ 161 imx_a53_plat_slot_config(false); 162 /* reverse the cluster level setting */ 163 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); 164 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); 165 166 /* clear PLAT/SCU power down */ 167 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), 168 EN_L2_WFI_PDN); 169 } 170 } 171 172 static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) 173 { 174 unsigned int n = id >> ISENABLER_SHIFT; 175 176 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 177 } 178 179 /* 180 * gic's clock will be gated in system suspend, so gic has no ability to 181 * to wakeup the system, we need to config the imr based on the irq 182 * enable status in gic, then gpc will monitor the wakeup irq 183 */ 184 void imx_set_sys_wakeup(unsigned int last_core, bool pdn) 185 { 186 uint32_t irq_mask; 187 uintptr_t gicd_base = PLAT_GICD_BASE; 188 189 if (pdn) 190 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), 191 IRQ_SRC_A53_WUP); 192 else 193 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, 194 A53_CORE_WUP_SRC(last_core)); 195 196 /* clear last core's IMR based on GIC's mask setting */ 197 for (int i = 0; i < IRQ_IMR_NUM; i++) { 198 if (pdn) 199 /* set the wakeup irq base GIC */ 200 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); 201 else 202 irq_mask = IMR_MASK_ALL; 203 204 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, 205 irq_mask); 206 } 207 } 208 209 #pragma weak imx_noc_slot_config 210 /* 211 * this function only need to be override by platform 212 * that support noc power down, for example: imx8mm. 213 * otherwize, keep it empty. 214 */ 215 void imx_noc_slot_config(bool pdn) 216 { 217 218 } 219 220 /* this is common for all imx8m soc */ 221 void imx_set_sys_lpm(unsigned int last_core, bool retention) 222 { 223 uint32_t val; 224 225 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 226 val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 227 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 228 229 if (retention) 230 val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 231 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 232 233 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 234 235 /* config the noc power down */ 236 imx_noc_slot_config(retention); 237 238 /* config wakeup irqs' mask in gpc */ 239 imx_set_sys_wakeup(last_core, retention); 240 } 241 242 void imx_set_rbc_count(void) 243 { 244 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 245 (0x8 << SLPCR_RBC_COUNT_SHIFT)); 246 } 247 248 void imx_clear_rbc_count(void) 249 { 250 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 251 (0x3f << SLPCR_RBC_COUNT_SHIFT)); 252 } 253