1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/console.h> 16 #include <drivers/mmc.h> 17 #include <lib/xlat_tables/xlat_mmu_helpers.h> 18 #include <lib/xlat_tables/xlat_tables_defs.h> 19 #include <lib/mmio.h> 20 #include <lib/optee_utils.h> 21 #include <lib/utils.h> 22 23 #include <imx_aips.h> 24 #include <imx_caam.h> 25 #include <imx_clock.h> 26 #include <imx_csu.h> 27 #include <imx_gpt.h> 28 #include <imx_io_mux.h> 29 #include <imx_uart.h> 30 #include <imx_snvs.h> 31 #include <imx_usdhc.h> 32 #include <imx_wdog.h> 33 34 #include "warp7_private.h" 35 36 #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 37 CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) 38 39 #define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 40 CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M) 41 42 #define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 43 CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ 44 CCM_TARGET_POST_PODF(2)) 45 46 #define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 47 CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) 48 49 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 50 CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) 51 52 uintptr_t plat_get_ns_image_entrypoint(void) 53 { 54 return WARP7_UBOOT_BASE; 55 } 56 57 static uint32_t warp7_get_spsr_for_bl32_entry(void) 58 { 59 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, 60 DISABLE_ALL_EXCEPTIONS); 61 } 62 63 static uint32_t warp7_get_spsr_for_bl33_entry(void) 64 { 65 return SPSR_MODE32(MODE32_svc, 66 plat_get_ns_image_entrypoint() & 0x1, 67 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 68 } 69 70 #ifndef AARCH32_SP_OPTEE 71 #error "Must build with OPTEE support included" 72 #endif 73 74 int bl2_plat_handle_post_image_load(unsigned int image_id) 75 { 76 int err = 0; 77 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 78 bl_mem_params_node_t *hw_cfg_mem_params = NULL; 79 80 bl_mem_params_node_t *pager_mem_params = NULL; 81 bl_mem_params_node_t *paged_mem_params = NULL; 82 83 assert(bl_mem_params); 84 85 switch (image_id) { 86 case BL32_IMAGE_ID: 87 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 88 assert(pager_mem_params); 89 90 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 91 assert(paged_mem_params); 92 93 err = parse_optee_header(&bl_mem_params->ep_info, 94 &pager_mem_params->image_info, 95 &paged_mem_params->image_info); 96 if (err != 0) 97 WARN("OPTEE header parse error.\n"); 98 99 /* 100 * When ATF loads the DTB the address of the DTB is passed in 101 * arg2, if an hw config image is present use the base address 102 * as DTB address an pass it as arg2 103 */ 104 hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); 105 106 bl_mem_params->ep_info.args.arg0 = 107 bl_mem_params->ep_info.args.arg1; 108 bl_mem_params->ep_info.args.arg1 = 0; 109 if (hw_cfg_mem_params) 110 bl_mem_params->ep_info.args.arg2 = 111 hw_cfg_mem_params->image_info.image_base; 112 else 113 bl_mem_params->ep_info.args.arg2 = 0; 114 bl_mem_params->ep_info.args.arg3 = 0; 115 bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry(); 116 break; 117 118 case BL33_IMAGE_ID: 119 /* AArch32 only core: OP-TEE expects NSec EP in register LR */ 120 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 121 assert(pager_mem_params); 122 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 123 124 /* BL33 expects to receive the primary CPU MPID (through r0) */ 125 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 126 bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry(); 127 break; 128 129 default: 130 /* Do nothing in default case */ 131 break; 132 } 133 134 return err; 135 } 136 137 void bl2_el3_plat_arch_setup(void) 138 { 139 /* Setup the MMU here */ 140 } 141 142 #define WARP7_UART1_TX_MUX \ 143 IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 144 145 #define WARP7_UART1_TX_FEATURES \ 146 (IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \ 147 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \ 148 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \ 149 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4) 150 151 #define WARP7_UART1_RX_MUX \ 152 IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 153 154 #define WARP7_UART1_RX_FEATURES \ 155 (IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \ 156 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \ 157 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \ 158 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4) 159 160 #define WARP7_UART6_TX_MUX \ 161 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA 162 163 #define WARP7_UART6_TX_FEATURES \ 164 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \ 165 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \ 166 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \ 167 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4) 168 169 #define WARP7_UART6_RX_MUX \ 170 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA 171 172 #define WARP7_UART6_RX_FEATURES \ 173 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \ 174 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \ 175 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \ 176 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4) 177 178 static void warp7_setup_pinmux(void) 179 { 180 /* Configure UART1 TX */ 181 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET, 182 WARP7_UART1_TX_MUX); 183 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET, 184 WARP7_UART1_TX_FEATURES); 185 186 /* Configure UART1 RX */ 187 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET, 188 WARP7_UART1_RX_MUX); 189 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET, 190 WARP7_UART1_RX_FEATURES); 191 192 /* Configure UART6 TX */ 193 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET, 194 WARP7_UART6_TX_MUX); 195 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET, 196 WARP7_UART6_TX_FEATURES); 197 198 /* Configure UART6 RX */ 199 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET, 200 WARP7_UART6_RX_MUX); 201 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET, 202 WARP7_UART6_RX_FEATURES); 203 } 204 205 static void warp7_usdhc_setup(void) 206 { 207 imx_usdhc_params_t params; 208 struct mmc_device_info info; 209 210 zeromem(¶ms, sizeof(imx_usdhc_params_t)); 211 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; 212 params.clk_rate = 25000000; 213 params.bus_width = MMC_BUS_WIDTH_8; 214 info.mmc_dev_type = MMC_IS_EMMC; 215 imx_usdhc_init(¶ms, &info); 216 } 217 218 static void warp7_setup_system_counter(void) 219 { 220 unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; 221 222 /* Set the frequency table index to our target frequency */ 223 write_cntfrq(freq); 224 225 /* Enable system counter @ frequency table index 0, halt on debug */ 226 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, 227 CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); 228 } 229 230 static void warp7_setup_wdog_clocks(void) 231 { 232 uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT; 233 234 imx_clock_set_wdog_clk_root_bits(wdog_en_bits); 235 imx_clock_enable_wdog(0); 236 imx_clock_enable_wdog(1); 237 imx_clock_enable_wdog(2); 238 imx_clock_enable_wdog(3); 239 } 240 241 static void warp7_setup_usb_clocks(void) 242 { 243 uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; 244 245 imx_clock_set_usb_clk_root_bits(usb_en_bits); 246 imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG); 247 imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK); 248 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); 249 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); 250 } 251 /* 252 * bl2_el3_early_platform_setup() 253 * MMU off 254 */ 255 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 256 u_register_t arg3, u_register_t arg4) 257 { 258 uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; 259 uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; 260 uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; 261 262 /* Initialize the AIPS */ 263 imx_aips_init(); 264 imx_csu_init(); 265 imx_snvs_init(); 266 imx_gpt_ops_init(GPT1_BASE_ADDR); 267 268 /* Initialize clocks, regulators, pin-muxes etc */ 269 imx_clock_init(); 270 imx_clock_enable_uart(0, uart1_en_bits); 271 imx_clock_enable_uart(5, uart6_en_bits); 272 imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); 273 warp7_setup_system_counter(); 274 warp7_setup_wdog_clocks(); 275 warp7_setup_usb_clocks(); 276 277 /* Setup pin-muxes */ 278 warp7_setup_pinmux(); 279 280 /* Init UART, storage and friends */ 281 console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ, 282 PLAT_WARP7_CONSOLE_BAUDRATE); 283 warp7_usdhc_setup(); 284 285 /* Open handles to persistent storage */ 286 plat_warp7_io_setup(); 287 288 /* Setup higher-level functionality CAAM, RTC etc */ 289 imx_caam_init(); 290 imx_wdog_init(); 291 292 /* Print out the expected memory map */ 293 VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); 294 VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); 295 VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); 296 VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); 297 VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); 298 VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); 299 } 300 301 /* 302 * bl2_platform_setup() 303 * MMU on - enabled by bl2_el3_plat_arch_setup() 304 */ 305 void bl2_platform_setup(void) 306 { 307 } 308