1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/mmc.h> 14 #include <lib/utils.h> 15 16 #include <imx_caam.h> 17 #include <imx_clock.h> 18 #include <imx_io_mux.h> 19 #include <imx_uart.h> 20 #include <imx_usdhc.h> 21 #include <imx7_def.h> 22 23 #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 24 CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) 25 26 #define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 27 CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M) 28 29 #define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 30 CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ 31 CCM_TARGET_POST_PODF(2)) 32 33 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 34 CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) 35 36 #define WARP7_UART1_TX_MUX \ 37 IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 38 39 #define WARP7_UART1_TX_FEATURES \ 40 (IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \ 41 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \ 42 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \ 43 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4) 44 45 #define WARP7_UART1_RX_MUX \ 46 IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 47 48 #define WARP7_UART1_RX_FEATURES \ 49 (IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \ 50 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \ 51 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \ 52 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4) 53 54 #define WARP7_UART6_TX_MUX \ 55 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA 56 57 #define WARP7_UART6_TX_FEATURES \ 58 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \ 59 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \ 60 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \ 61 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4) 62 63 #define WARP7_UART6_RX_MUX \ 64 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA 65 66 #define WARP7_UART6_RX_FEATURES \ 67 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \ 68 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \ 69 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \ 70 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4) 71 72 static void warp7_setup_pinmux(void) 73 { 74 /* Configure UART1 TX */ 75 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET, 76 WARP7_UART1_TX_MUX); 77 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET, 78 WARP7_UART1_TX_FEATURES); 79 80 /* Configure UART1 RX */ 81 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET, 82 WARP7_UART1_RX_MUX); 83 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET, 84 WARP7_UART1_RX_FEATURES); 85 86 /* Configure UART6 TX */ 87 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET, 88 WARP7_UART6_TX_MUX); 89 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET, 90 WARP7_UART6_TX_FEATURES); 91 92 /* Configure UART6 RX */ 93 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET, 94 WARP7_UART6_RX_MUX); 95 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET, 96 WARP7_UART6_RX_FEATURES); 97 } 98 99 static void warp7_usdhc_setup(void) 100 { 101 imx_usdhc_params_t params; 102 struct mmc_device_info info; 103 104 zeromem(¶ms, sizeof(imx_usdhc_params_t)); 105 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; 106 params.clk_rate = 25000000; 107 params.bus_width = MMC_BUS_WIDTH_8; 108 info.mmc_dev_type = MMC_IS_EMMC; 109 imx_usdhc_init(¶ms, &info); 110 } 111 112 static void warp7_setup_usb_clocks(void) 113 { 114 uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; 115 116 imx_clock_set_usb_clk_root_bits(usb_en_bits); 117 imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG); 118 imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK); 119 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); 120 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); 121 } 122 123 void imx7_platform_setup(u_register_t arg1, u_register_t arg2, 124 u_register_t arg3, u_register_t arg4) 125 { 126 uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; 127 uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; 128 uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; 129 130 /* Initialize clocks etc */ 131 imx_clock_enable_uart(0, uart1_en_bits); 132 imx_clock_enable_uart(5, uart6_en_bits); 133 134 imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); 135 136 warp7_setup_usb_clocks(); 137 138 /* Setup pin-muxes */ 139 warp7_setup_pinmux(); 140 141 warp7_usdhc_setup(); 142 } 143