1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <mmc.h> 14 #include <mmio.h> 15 #include <optee_utils.h> 16 #include <platform_def.h> 17 #include <utils.h> 18 #include <xlat_mmu_helpers.h> 19 #include <xlat_tables_defs.h> 20 #include <imx_aips.h> 21 #include <imx_caam.h> 22 #include <imx_clock.h> 23 #include <imx_csu.h> 24 #include <imx_gpt.h> 25 #include <imx_io_mux.h> 26 #include <imx_uart.h> 27 #include <imx_snvs.h> 28 #include <imx_usdhc.h> 29 #include <imx_wdog.h> 30 #include "warp7_private.h" 31 32 #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 33 CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) 34 35 #define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 36 CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M) 37 38 #define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 39 CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ 40 CCM_TARGET_POST_PODF(2)) 41 42 #define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 43 CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) 44 45 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 46 CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) 47 48 uintptr_t plat_get_ns_image_entrypoint(void) 49 { 50 return WARP7_UBOOT_BASE; 51 } 52 53 static uint32_t warp7_get_spsr_for_bl32_entry(void) 54 { 55 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, 56 DISABLE_ALL_EXCEPTIONS); 57 } 58 59 static uint32_t warp7_get_spsr_for_bl33_entry(void) 60 { 61 return SPSR_MODE32(MODE32_svc, 62 plat_get_ns_image_entrypoint() & 0x1, 63 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 64 } 65 66 #ifndef AARCH32_SP_OPTEE 67 #error "Must build with OPTEE support included" 68 #endif 69 70 int bl2_plat_handle_post_image_load(unsigned int image_id) 71 { 72 int err = 0; 73 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 74 bl_mem_params_node_t *hw_cfg_mem_params = NULL; 75 76 bl_mem_params_node_t *pager_mem_params = NULL; 77 bl_mem_params_node_t *paged_mem_params = NULL; 78 79 assert(bl_mem_params); 80 81 switch (image_id) { 82 case BL32_IMAGE_ID: 83 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 84 assert(pager_mem_params); 85 86 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 87 assert(paged_mem_params); 88 89 err = parse_optee_header(&bl_mem_params->ep_info, 90 &pager_mem_params->image_info, 91 &paged_mem_params->image_info); 92 if (err != 0) 93 WARN("OPTEE header parse error.\n"); 94 95 /* 96 * When ATF loads the DTB the address of the DTB is passed in 97 * arg2, if an hw config image is present use the base address 98 * as DTB address an pass it as arg2 99 */ 100 hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); 101 102 bl_mem_params->ep_info.args.arg0 = 103 bl_mem_params->ep_info.args.arg1; 104 bl_mem_params->ep_info.args.arg1 = 0; 105 if (hw_cfg_mem_params) 106 bl_mem_params->ep_info.args.arg2 = 107 hw_cfg_mem_params->image_info.image_base; 108 else 109 bl_mem_params->ep_info.args.arg2 = 0; 110 bl_mem_params->ep_info.args.arg3 = 0; 111 bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry(); 112 break; 113 114 case BL33_IMAGE_ID: 115 /* AArch32 only core: OP-TEE expects NSec EP in register LR */ 116 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 117 assert(pager_mem_params); 118 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 119 120 /* BL33 expects to receive the primary CPU MPID (through r0) */ 121 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 122 bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry(); 123 break; 124 125 default: 126 /* Do nothing in default case */ 127 break; 128 } 129 130 return err; 131 } 132 133 void bl2_el3_plat_arch_setup(void) 134 { 135 /* Setup the MMU here */ 136 } 137 138 #define WARP7_UART1_TX_MUX \ 139 IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 140 141 #define WARP7_UART1_TX_FEATURES \ 142 (IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \ 143 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \ 144 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \ 145 IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4) 146 147 #define WARP7_UART1_RX_MUX \ 148 IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 149 150 #define WARP7_UART1_RX_FEATURES \ 151 (IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \ 152 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \ 153 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \ 154 IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4) 155 156 #define WARP7_UART6_TX_MUX \ 157 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA 158 159 #define WARP7_UART6_TX_FEATURES \ 160 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \ 161 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \ 162 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \ 163 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4) 164 165 #define WARP7_UART6_RX_MUX \ 166 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA 167 168 #define WARP7_UART6_RX_FEATURES \ 169 (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \ 170 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \ 171 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \ 172 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4) 173 174 static void warp7_setup_pinmux(void) 175 { 176 /* Configure UART1 TX */ 177 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET, 178 WARP7_UART1_TX_MUX); 179 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET, 180 WARP7_UART1_TX_FEATURES); 181 182 /* Configure UART1 RX */ 183 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET, 184 WARP7_UART1_RX_MUX); 185 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET, 186 WARP7_UART1_RX_FEATURES); 187 188 /* Configure UART6 TX */ 189 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET, 190 WARP7_UART6_TX_MUX); 191 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET, 192 WARP7_UART6_TX_FEATURES); 193 194 /* Configure UART6 RX */ 195 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET, 196 WARP7_UART6_RX_MUX); 197 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET, 198 WARP7_UART6_RX_FEATURES); 199 } 200 201 static void warp7_usdhc_setup(void) 202 { 203 imx_usdhc_params_t params; 204 struct mmc_device_info info; 205 206 zeromem(¶ms, sizeof(imx_usdhc_params_t)); 207 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; 208 params.clk_rate = 25000000; 209 params.bus_width = MMC_BUS_WIDTH_8; 210 info.mmc_dev_type = MMC_IS_EMMC; 211 imx_usdhc_init(¶ms, &info); 212 } 213 214 static void warp7_setup_system_counter(void) 215 { 216 unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; 217 218 /* Set the frequency table index to our target frequency */ 219 write_cntfrq(freq); 220 221 /* Enable system counter @ frequency table index 0, halt on debug */ 222 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, 223 CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); 224 } 225 226 static void warp7_setup_wdog_clocks(void) 227 { 228 uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT; 229 230 imx_clock_set_wdog_clk_root_bits(wdog_en_bits); 231 imx_clock_enable_wdog(0); 232 imx_clock_enable_wdog(1); 233 imx_clock_enable_wdog(2); 234 imx_clock_enable_wdog(3); 235 } 236 237 static void warp7_setup_usb_clocks(void) 238 { 239 uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; 240 241 imx_clock_set_usb_clk_root_bits(usb_en_bits); 242 imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG); 243 imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK); 244 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); 245 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); 246 } 247 /* 248 * bl2_el3_early_platform_setup() 249 * MMU off 250 */ 251 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 252 u_register_t arg3, u_register_t arg4) 253 { 254 uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; 255 uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; 256 uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; 257 258 /* Initialize the AIPS */ 259 imx_aips_init(); 260 imx_csu_init(); 261 imx_snvs_init(); 262 imx_gpt_ops_init(GPT1_BASE_ADDR); 263 264 /* Initialize clocks, regulators, pin-muxes etc */ 265 imx_clock_init(); 266 imx_clock_enable_uart(0, uart1_en_bits); 267 imx_clock_enable_uart(5, uart6_en_bits); 268 imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); 269 warp7_setup_system_counter(); 270 warp7_setup_wdog_clocks(); 271 warp7_setup_usb_clocks(); 272 273 /* Setup pin-muxes */ 274 warp7_setup_pinmux(); 275 276 /* Init UART, storage and friends */ 277 console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ, 278 PLAT_WARP7_CONSOLE_BAUDRATE); 279 warp7_usdhc_setup(); 280 281 /* Open handles to persistent storage */ 282 plat_warp7_io_setup(); 283 284 /* Setup higher-level functionality CAAM, RTC etc */ 285 imx_caam_init(); 286 imx_wdog_init(); 287 288 /* Print out the expected memory map */ 289 VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); 290 VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); 291 VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); 292 VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); 293 VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); 294 VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); 295 } 296 297 /* 298 * bl2_platform_setup() 299 * MMU on - enabled by bl2_el3_plat_arch_setup() 300 */ 301 void bl2_platform_setup(void) 302 { 303 } 304