1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/mmc.h> 14 #include <lib/utils.h> 15 16 #include <imx_caam.h> 17 #include <imx_clock.h> 18 #include <imx_io_mux.h> 19 #include <imx_uart.h> 20 #include <imx_usdhc.h> 21 #include <imx7_def.h> 22 23 #define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 24 CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M) 25 26 #define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 27 CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ 28 CCM_TARGET_POST_PODF(2)) 29 30 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ 31 CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) 32 33 #define PICOPI_UART5_RX_MUX \ 34 IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA 35 36 #define PICOPI_UART5_TX_MUX \ 37 IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA 38 39 #define PICOPI_SD3_FEATURES \ 40 (IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K | \ 41 IOMUXC_SW_PAD_CTL_PAD_SD3_PE | \ 42 IOMUXC_SW_PAD_CTL_PAD_SD3_HYS | \ 43 IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \ 44 IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6) 45 46 static void picopi_setup_pinmux(void) 47 { 48 /* Configure UART5 TX */ 49 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET, 50 PICOPI_UART5_TX_MUX); 51 /* Configure UART5 RX */ 52 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET, 53 PICOPI_UART5_RX_MUX); 54 55 /* Configure USDHC3 */ 56 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0); 57 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0); 58 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0); 59 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0); 60 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0); 61 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0); 62 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0); 63 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0); 64 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0); 65 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0); 66 imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET, 67 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B); 68 69 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET, 70 PICOPI_SD3_FEATURES); 71 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET, 72 PICOPI_SD3_FEATURES); 73 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET, 74 PICOPI_SD3_FEATURES); 75 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET, 76 PICOPI_SD3_FEATURES); 77 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET, 78 PICOPI_SD3_FEATURES); 79 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET, 80 PICOPI_SD3_FEATURES); 81 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET, 82 PICOPI_SD3_FEATURES); 83 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET, 84 PICOPI_SD3_FEATURES); 85 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET, 86 PICOPI_SD3_FEATURES); 87 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET, 88 PICOPI_SD3_FEATURES); 89 imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET, 90 PICOPI_SD3_FEATURES); 91 } 92 93 static void picopi_usdhc_setup(void) 94 { 95 imx_usdhc_params_t params; 96 struct mmc_device_info info; 97 98 zeromem(¶ms, sizeof(imx_usdhc_params_t)); 99 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; 100 params.clk_rate = 25000000; 101 params.bus_width = MMC_BUS_WIDTH_8; 102 info.mmc_dev_type = MMC_IS_EMMC; 103 imx_usdhc_init(¶ms, &info); 104 } 105 106 static void picopi_setup_usb_clocks(void) 107 { 108 uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; 109 110 imx_clock_set_usb_clk_root_bits(usb_en_bits); 111 imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG); 112 imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK); 113 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); 114 imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); 115 } 116 117 void imx7_platform_setup(u_register_t arg1, u_register_t arg2, 118 u_register_t arg3, u_register_t arg4) 119 { 120 uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT; 121 uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1; 122 123 /* Initialize clocks etc */ 124 imx_clock_enable_uart(4, uart5_en_bits); 125 imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); 126 127 picopi_setup_usb_clocks(); 128 129 /* Setup pin-muxes */ 130 picopi_setup_pinmux(); 131 132 picopi_usdhc_setup(); 133 } 134