1*ff2743e5SAnson Huang /* 2*ff2743e5SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*ff2743e5SAnson Huang * 4*ff2743e5SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*ff2743e5SAnson Huang */ 6*ff2743e5SAnson Huang 7*ff2743e5SAnson Huang #include <types.h> 8*ff2743e5SAnson Huang 9*ff2743e5SAnson Huang #define MU_ATR0_OFFSET1 0x0 10*ff2743e5SAnson Huang #define MU_ARR0_OFFSET1 0x10 11*ff2743e5SAnson Huang #define MU_ASR_OFFSET1 0x20 12*ff2743e5SAnson Huang #define MU_ACR_OFFSET1 0x24 13*ff2743e5SAnson Huang #define MU_TR_COUNT1 4 14*ff2743e5SAnson Huang #define MU_RR_COUNT1 4 15*ff2743e5SAnson Huang 16*ff2743e5SAnson Huang #define MU_CR_GIEn_MASK1 (0xF << 28) 17*ff2743e5SAnson Huang #define MU_CR_RIEn_MASK1 (0xF << 24) 18*ff2743e5SAnson Huang #define MU_CR_TIEn_MASK1 (0xF << 20) 19*ff2743e5SAnson Huang #define MU_CR_GIRn_MASK1 (0xF << 16) 20*ff2743e5SAnson Huang #define MU_CR_NMI_MASK1 (1 << 3) 21*ff2743e5SAnson Huang #define MU_CR_Fn_MASK1 0x7 22*ff2743e5SAnson Huang 23*ff2743e5SAnson Huang #define MU_SR_TE0_MASK1 (1 << 23) 24*ff2743e5SAnson Huang #define MU_SR_RF0_MASK1 (1 << 27) 25*ff2743e5SAnson Huang #define MU_CR_RIE0_MASK1 (1 << 27) 26*ff2743e5SAnson Huang #define MU_CR_GIE0_MASK1 (1 << 31) 27*ff2743e5SAnson Huang 28*ff2743e5SAnson Huang #define MU_TR_COUNT 4 29*ff2743e5SAnson Huang #define MU_RR_COUNT 4 30*ff2743e5SAnson Huang 31*ff2743e5SAnson Huang void MU_Init(uint32_t base); 32*ff2743e5SAnson Huang void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg); 33*ff2743e5SAnson Huang void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg); 34*ff2743e5SAnson Huang void MU_EnableGeneralInt(uint32_t base, uint32_t index); 35*ff2743e5SAnson Huang void MU_EnableRxFullInt(uint32_t base, uint32_t index); 36