1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 9 #include "imx8_mu.h" 10 11 void MU_EnableRxFullInt(uint32_t base, uint32_t index) 12 { 13 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 14 15 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 16 reg |= MU_CR_RIE0_MASK1 >> index; 17 mmio_write_32(base + MU_ACR_OFFSET1, reg); 18 } 19 20 void MU_EnableGeneralInt(uint32_t base, uint32_t index) 21 { 22 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 23 24 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 25 reg |= MU_CR_GIE0_MASK1 >> index; 26 mmio_write_32(base + MU_ACR_OFFSET1, reg); 27 } 28 29 void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg) 30 { 31 uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; 32 33 /* Wait TX register to be empty. */ 34 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 35 ; 36 mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg); 37 } 38 39 void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg) 40 { 41 uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; 42 43 /* Wait RX register to be full. */ 44 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 45 ; 46 *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4)); 47 } 48 49 void MU_Init(uint32_t base) 50 { 51 uint32_t reg; 52 53 reg = mmio_read_32(base + MU_ACR_OFFSET1); 54 /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 55 reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 56 | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 57 mmio_write_32(base + MU_ACR_OFFSET1, reg); 58 } 59