1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 9 #include "imx8_mu.h" 10 11 void MU_Resume(uint32_t base) 12 { 13 uint32_t reg, i; 14 15 reg = mmio_read_32(base + MU_ACR_OFFSET1); 16 /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 17 reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 18 | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 19 mmio_write_32(base + MU_ACR_OFFSET1, reg); 20 21 /* Enable all RX interrupts */ 22 for (i = 0; i < MU_RR_COUNT; i++) 23 MU_EnableRxFullInt(base, i); 24 } 25 26 void MU_EnableRxFullInt(uint32_t base, uint32_t index) 27 { 28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 29 30 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 31 reg |= MU_CR_RIE0_MASK1 >> index; 32 mmio_write_32(base + MU_ACR_OFFSET1, reg); 33 } 34 35 void MU_EnableGeneralInt(uint32_t base, uint32_t index) 36 { 37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 38 39 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 40 reg |= MU_CR_GIE0_MASK1 >> index; 41 mmio_write_32(base + MU_ACR_OFFSET1, reg); 42 } 43 44 void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg) 45 { 46 uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; 47 48 /* Wait TX register to be empty. */ 49 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 50 ; 51 mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg); 52 } 53 54 void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg) 55 { 56 uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; 57 58 /* Wait RX register to be full. */ 59 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 60 ; 61 *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4)); 62 } 63 64 void MU_Init(uint32_t base) 65 { 66 uint32_t reg; 67 68 reg = mmio_read_32(base + MU_ACR_OFFSET1); 69 /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 70 reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 71 | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 72 mmio_write_32(base + MU_ACR_OFFSET1, reg); 73 } 74